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Particle graphics on reconfigurable hardware

John S. Beeckler, Warren J. Gross
2008 ACM Transactions on Reconfigurable Technology and Systems  
This article presents the design and implementation of a hardware particle graphics engine for accelerating real-time particle graphics simulations.  ...  The FPGA particle engine processes million-particle systems at a rate from 47 to 112 million particles per second, which represents one to two orders of magnitude speedup over a 2.8 GHz CPU.  ...  It must be easy to reconfigure the accelerator to change the effect. This is one reason why a programmable hardware accelerator like a GPU or FPGA is required and a custom chip is not suitable.  ... 
doi:10.1145/1391732.1391735 fatcat:yrg5xhyrojfsnftze3236vjugi

Applications of Small-Scale Reconfigurability to Graphics Processors [chapter]

Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron
2006 Lecture Notes in Computer Science  
We explore the application of Small-Scale Reconfigurability (SSR) to graphics hardware.  ...  fragment shader performance with a minimal impact on chip area.  ...  Acknowledgments We would like to thank John Lach for his input on SSR and Peter Djeu for his collaboration on Chromium extensions.  ... 
doi:10.1007/11802839_14 fatcat:leazm3pcefgypcwjdudc2peona

FPGA implementation of particle swarm optimization for Bayesian network learning

Matthew J. Hibbard, Eric R. Peskin, Ferat Sahin
2013 Computers & electrical engineering  
This makes BN learning a candidate for acceleration using reconfigurable hardware such as fieldprogrammable gate arrays (FPGAs).  ...  We present a FPGA-based implementation of BN learning using particle-swarm optimization (PSO).  ...  FPGAs are a type of reconfigurable hardware that can achieve better performance than software while allowing more flexibility than hardware [9] .  ... 
doi:10.1016/j.compeleceng.2013.07.018 fatcat:zjn5iglgxzdxnkfpjdms6lf674

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

J. S. Kim, P. Mangalagiri, K. Irick, M. Kandemir, V. Narayanan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun
2007 2007 International Conference on Field Programmable Logic and Applications  
Our results demonstrate that TANOR generates hardware accelerator that are competitive with existing custom accelerator.  ...  In this paper, we describe TANOR an automated tool targeted for designing hardware accelerators for the class of N-body interaction problems.  ...  CONCLUSION AND FUTURE WORK We have developed a tool to automatically generate hardware for accelerating N-body simulation on reconfigurable platform.  ... 
doi:10.1109/fpl.2007.4380627 dblp:conf/fpl/KimMIKNSDCPS07 fatcat:6qr4ixyaczewxordrd64rkm2im

A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms [chapter]

Markus Happe, Enno Lübbers, Marco Platzner
2009 Lecture Notes in Computer Science  
We demonstrate the framework on a case study for visual object tracking and evaluate the performance of different hardware/software partitionings.  ...  The framework is based on the multithreaded reconfigurable operating system ReconOS which allows for an easy repartitioning of threads between hard-and software.  ...  Figure 1 graphically represents one iteration.  ... 
doi:10.1007/978-3-642-00641-8_45 fatcat:bkxv2pkhzvazfnayjs7wsftrxe

UbiManager: A Software Tool for Managing Ubichips

Yann Thoma, Andres Upegui
2008 2008 NASA/ESA Conference on Adaptive Hardware and Systems  
NASA/ESA Conference on Adaptive Hardware and Systems 978-0-7695-3166-3/08 $25.00  ...  The ubichip has been developed in the framework of Perplexus, a European project that aims to develop a scalable hardware platform made of bio-inspired custom reconfigurable devices for simulating large-scale  ...  CONCLUSIONS The Perplexus ubidule is a reconfigurable hardware platform for the simulation of complex systems.  ... 
doi:10.1109/ahs.2008.39 dblp:conf/ahs/ThomaU08 fatcat:a6stpdosojgwnegd65ztkfwika

Small-scale reconfigurability for improved performance and double-precision in graphics hardware

K. Dale, J. W. Sheaffer, V. Vijay Kumar, D. P. Luebke, G. Humphreys, K. Skadron
2007 International journal of electronics (Print)  
We explore the application of Small-Scale Reconfigurability (SSR) to graphics hardware.  ...  shader performance with a minimal impact on chip area.  ...  Acknowledgments We would like to thank John Lach for his input on SSR and Peter Djeu for his collaboration on Chromium extensions.  ... 
doi:10.1080/00207210701308500 fatcat:7yact76lvnazhde6erlhymqbae

iMASS: Computational NRF Spectra Signal from Geant4

John Perry, Shanjie Xiao, Tatjana Jevremovic
2008 2008 20th IEEE International Conference on Tools with Artificial Intelligence  
This paper introduces the preliminary results related to the Monte Carlo simulation of NRF spectra signal and the importance of reconfigurable computational technique to accelerate Monte Carlo iMASS computational  ...  A specific hardware chip will be designed based on the reconfigurable computation technique.  ...  The graphics can be generated without hardware acceleration in an OpenGL environment. The visualization capability also supports other graphical processes apart from OpenGL.  ... 
doi:10.1109/ictai.2008.94 dblp:conf/ictai/PerryXJ08 fatcat:vzuzqxpsazbphbb3m6e4dfa24i

ReMod3D: A high-performance simulator for autonomous, self-reconfigurable robots

Thomas Collins, Nadeesha Oliver Ranasinghe, Wei-Min Shen
2013 2013 IEEE/RSJ International Conference on Intelligent Robots and Systems  
RM3D also simulates inter-module dock connection breakage, something novel for self-reconfigurable robot simulators.  ...  self-reconfigurable simulators while, at the same time, allowing for realistic module structures, complex environments, and high physical simulation fidelity.  ...  RELATED WORK Building simulators for self-reconfigurable robots is a challenging endeavor because it requires knowledge of robotics, 3D graphics, the inner workings of physics engines, and software engineering  ... 
doi:10.1109/iros.2013.6696970 dblp:conf/iros/CollinsRS13 fatcat:wbmfkjvcqndmjc6n2hmcnjblde

Energy-efficient GPU design with reconfigurable in-package graphics memory

Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
2012 Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design - ISLPED '12  
We propose an energy-efficient reconfigurable in-package graphics memory design that integrates wide-interface graphics DRAMs with GPU on a silicon interposer.  ...  Furthermore, we design a reconfigurable memory interface and propose two reconfiguration mechanisms to optimize system energy efficiency and throughput.  ...  On top of the reconfigurable memory interface hardware, we further propose two reconfiguration mechanisms, EOpt and PerfOpt, that optimize system energy efficiency and performance (in terms of throughput  ... 
doi:10.1145/2333660.2333752 dblp:conf/islped/ZhaoSLX12 fatcat:t3wqi5ejmvcbxjzslkggwgcn6i

Embedded Intelligence on Chip: Some FPGAbased Design Experiences [chapter]

Felix Moreno, Ignacio Lopez, Ricardo Sanz, Ruben Salvador, Jaime Alarco
2010 Pattern Recognition Recent Advances  
In order to maintain the processing speed of a TNN in hardware and its versatility in simulations, the reconfiguration of the neural network on its different hardware levels has to be possible (Reconfiguration  ...  In order to maintain the processing speed of a TNN in hardware and its versatility in simulations, the reconfiguration of the neural network on its different hardware levels has to be possible (Reconfiguration  ...  /patternrecognition-recent-advances/embedded-intelligence-on-chip-some-fpgabased-design-experiences  ... 
doi:10.5772/9366 fatcat:43vbnojqanahtfsn7v5qqldfni

Reconfigurable Instrumentation Technologies, Architectures and Trends

Rok Uršič
2002 AIP Conference Proceedings  
Reconfigurability is liberating radio-based instrumentation devices from chronic dependency on hard-wired characteristics of the radio front end.  ...  Today the evolution toward practical "reconfigurable" instrumentation is accelerating through a combination of approaches.  ...  This is not a comprehensive overview or a tutorial on reconfigurability. It is a vision that builds on my experience.  ... 
doi:10.1063/1.1524399 fatcat:quuhzg5xyzbgzc7ji75w3ozmke

Towards a holistic CAD platform for nanotechnologies

E. Kolonis, M. Nicolaidis
2008 Microelectronics Journal  
The paper presents a work in progress on this direction.  ...  Research on nanotechnologies is actively conducted in a world-wide effort to develop new technologies able to maintain the Moore's law.  ...  However, efficient exploitation of the hardware resources depends on the architecture of this hardware and the way a target application is mapped on it.  ... 
doi:10.1016/j.mejo.2007.08.005 fatcat:w6kkphqbovco3cdujbmnoukg4q

Reconfigurable Computing for Space [chapter]

Donohoe, Gregory W., Lyke James
2010 Aerospace Technologies Advancements  
Reconfigurable computers may be implemented on specially-designed hardware, or on Field Programmable Gate Arrays (FPGAs).  ...  Reconfigurability can help designers meet challenges (1) and (2) above by enabling hardware to be reconfigured for different phases of a computational task, resulting in smaller size, lower weight, and  ...  Reconfigurable Computing for Space, Aerospace Technologies Advancements, Thawar T.  ... 
doi:10.5772/6939 fatcat:qiy3vly24ndm3eikjutrfzwceu

Building Image Feature Kinetics for Cement Hydration Using Gene Expression Programming With Similarity Weight Tournament Selection

Lin Wang, Bo Yang, Shoude Wang, Zhifeng Liang
2015 IEEE Transactions on Evolutionary Computation  
D.: On the Evolution of Hardware Circuits via Reconfigurable Architectures.  ...  D.: On the Evolution of Hardware Circuits via Reconfigurable Architectures.  ... 
doi:10.1109/tevc.2014.2367111 fatcat:dsfdt3ngn5htfdg4ydmofrqznm
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