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A Fast Online Task Placement Algorithm for Three-dimensional Dynamic Partial Reconfigurable Devices

Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe
2020 IEEE Access  
Since the task placement is only one step in the overall process of online task processing for dynamic partial reconfigurable devices, as part of our future work, a scheduling order based on task priority  ...  and update unoccupied 3D resources [17] . 3) Online Task Placement Model When a new task arrives at the system based on a given arriving time interval, a task with a closer deadline between the new  ...  When tasks are placed on the 3D DPR device, the Eq. 8 is satisfied, which was already proved in [11] .  ... 
doi:10.1109/access.2020.2975254 fatcat:mz4sy44f5bed7dq6yhayqe52ai

Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs

Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao
2008 2008 IEEE International Conference on Computer Design  
Following that we step further and integrate our solution in to a floorplanner to generate placements for wireless systems which can systematically hide or reduce reconfiguration time overhead.  ...  Software Defined Radio (SDR) base stations can compensate for failures in disaster scenarios by assimilating different communication technologies.  ...  In [15] the authors propose online scheduling system that allocates tasks to a block partitioned reconfigurable device. III.  ... 
doi:10.1109/iccd.2008.4751871 dblp:conf/iccd/GholamipourBB08 fatcat:swe4tvg7wrgwvgyiroidck6k64

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

Florian Dittmann, Marcelo Gotz, Achim Rettberg
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration.  ...  When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required  ...  The authors of [10] present HW/SW co-synthesis for run-time reconfigurable systems, relying on an exact algorithm (ILP) and a KLFM-based approach.  ... 
doi:10.1109/ipdps.2007.370388 dblp:conf/ipps/DittmannGR07 fatcat:pzitl37wtfearcymr4bo5l2nie

A self-adaptive on-line task placement algorithm for partially reconfigurable systems

Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels, Roel Meeuws
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
In this paper, we propose an algorithm to handle this on-line, run-time task placement problem.  ...  in terms of task rejection number, placement quality 1 and execution time.  ...  Acknowledgment: This work is sponsored by the hArtes project (IST-035143) supported by the Sixth Framework Programme of the European Community under the thematic area "Embedded Systems".  ... 
doi:10.1109/ipdps.2008.4536505 dblp:conf/ipps/LuMGBM08 fatcat:homolwognjdgnoiwbzkelzzaqi

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration

Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The execution time of our heuristic is very reasonable-task graphs with hundreds of nodes are processed (partitioned, scheduled, and placed) in a couple of minutes.  ...  However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their helpful comments that significantly improved the clarity of their paper.  ... 
doi:10.1109/tvlsi.2006.886411 fatcat:jjwx65abcnbmddeksuov7fwn5m

Efficient algorithms for identifying all maximal isothetic empty rectangles in VLSI layout design [chapter]

Subhas C Nandy, Bhargab B Bhattacharya, Sibabrata Ray
1990 Lecture Notes in Computer Science  
[AT03] presented an online placer for a 1D model of a reconfigurable device. Their algorithm selects a placement for a task as if in a 2D model.  ...  ), while in the online version, the scheduler has no information about tasks to arrive in the future.  ...  In the area of scheduling we proposed an algorithm based on dividing the chip into different regions and assigning tasks to regions based on their width.  ... 
doi:10.1007/3-540-53487-3_50 fatcat:twijq2vqqrfl5kh44jq6blmfx4

A dynamical evolution approach to high placement performance and low fault-tolerant cost for bio-inspired self-repairing hardware

Liu Xiubin, Li Duo, Li Yue
2020 IEEE Access  
The algebra structure of placement transformation inspires us to develop a task decomposition method to make full use of online computing resources.  ...  In conclusion, current methods are conducted based on a one-step placement transformation, and only a few processing elements are used to execute the calculation task (Table 1) .  ... 
doi:10.1109/access.2020.3006121 fatcat:ugygfcfveba3bhxmwznprf5poa

A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures

Marco Giorgetta, Marco Santambrogio, Donatella Sciuto, Paola Spoletini
2006 2006 IFIP International Conference on Very Large Scale Integration  
Designing systems mapped onto FPGAs that foresee a dynamic reconfiguration of the application is a difficult task.  ...  The new algorithm has been experimented on the Xilinx-based architecture defined to support dynamic reconfigurability [2] .  ...  The algorithm proposed in this paper is part of the Caronte methodology, [2, 14] for the dynamic reconfiguration of an embedded system introducing a partial dynamic reconfiguration degree in the design  ... 
doi:10.1109/vlsisoc.2006.313267 dblp:conf/vlsi/GiorgettaSSS06 fatcat:42wbibisefbtpdzahflqep73xq

Minimal Cost Reconfiguration of Data Placement in Storage Area Network [chapter]

Hadas Shachnai, Gal Tamir, Tami Tamir
2010 Lecture Notes in Computer Science  
We then develop algorithms which achieve the optimal cost by using servers whose load capacities are increased by O(1), in particular, by factor 1 +δ for any small 0 < δ < 1 when the number of servers  ...  The problem shows up also in production planning, preemptive scheduling with set-up costs, and dynamic placement of Web applications.  ...  Acknowledgments We thank two anonymous referees for many valuable comments and suggestions.  ... 
doi:10.1007/978-3-642-12450-1_21 fatcat:2t5lpkzmoffzxl5myvxflwrhcq

Minimal cost reconfiguration of data placement in a storage area network

Hadas Shachnai, Gal Tamir, Tami Tamir
2012 Theoretical Computer Science  
We then develop algorithms which achieve the optimal cost by using servers whose load capacities are increased by O(1), in particular, by factor 1 +δ for any small 0 < δ < 1 when the number of servers  ...  The problem shows up also in production planning, preemptive scheduling with set-up costs, and dynamic placement of Web applications.  ...  Acknowledgments We thank two anonymous referees for many valuable comments and suggestions.  ... 
doi:10.1016/j.tcs.2012.06.018 fatcat:qauuii6nzbf6lemauzwlpifua4

Fast, Anytime Motion Planning for Prehensile Manipulation in Clutter

Andrew Kimmel, Rahul Shome, Zakary Littlefield, Kostas Bekris
2018 2018 IEEE-RAS 18th International Conference on Humanoid Robots (Humanoids)  
Then, an informed sampling-based planner for the entire arm uses Jacobian-based steering to reach promising end effector poses given the task space guidance.  ...  This paper evaluates the proposed method against alternatives in picking or placing tasks among varying amounts of clutter for a variety of robotic manipulators with different end-effectors.  ...  DISCUSSION This paper presented the Jacobian Informed Search Tree (JIST) algorithm, which is an asymptotically optimal, informed sampling-based planner for controlling an arm in densely cluttered scenes  ... 
doi:10.1109/humanoids.2018.8624939 dblp:conf/humanoids/KimmelSLB18 fatcat:pykzy63vl5cn3misds5qiykhgq

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Adewale Adetomi, Godwin Enemali, Xabier Iturbe, Tughrul Arslan, Didier Keymeulen
2018 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
Authors in [73] , proposed runtime placement algorithms for heterogeneous reconfigurable platforms.  ...  Task Reuse to Circumvent Large Reconfiguration Overhead on COTS FPGAs Online placement management systems on reconfiguration hardware such as COTS FPGAs must circumvent constraints associated with the  ... 
doi:10.1109/ahs.2018.8541369 dblp:conf/ahs/AdetomiEIAK18 fatcat:kr7xdsvbaveqxplr6iwpdpx4me

Optimal self assembly of modular manipulators with active and passive modules

Seung-kook Yun, Daniela Rus
2011 Autonomous Robots  
In this thesis, we describe algorithms to build self-assembling robot systems composed of active modular robots and passive bars.  ...  We prove that the same optimalityquadratic competitive ratioas for the static graph can be achieved for the algorithms. We demonstrate how this algorithm can be used to build truss-like structures.  ...  In each case, task information is given to the robots in the form of a command stack. The robots decide which role to play based on the task specification and its location.  ... 
doi:10.1007/s10514-011-9236-1 fatcat:utxmld276fbrxeai2onzq7gvqq

Acceleration of real-time Proximity Query for dynamic active constraints

Thomas C.P. Chau, Ka-Wai Kwok, Gary C.T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk
2013 2013 International Conference on Field-Programmable Technology (FPT)  
We optimise the proposed PQ for reconfigurable hardware by function transformation and reduced precision, resulting in a novel data structure and memory architecture for data streaming while maintaining  ...  Run-time reconfiguration is adopted for dynamic precision optimisation.  ...  We then map the optimised algorithm to a reconfigurable system with four Virtex-6 FPGAs and 12 CPU cores.  ... 
doi:10.1109/fpt.2013.6718355 dblp:conf/fpt/ChauKCTLTCL13 fatcat:zelw6lklqfbgtavhhbzdkmg32m

A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System

Lan-Da Van, Ten-Yao Sheu
2011 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
In terms of the number of multiplications for transforms, the reduction can be attained by 27.5% and 60.27% for level-1 and level-2 subdivision, respectively.  ...  According to the low-complexity subdivision algorithm, one reconfigurable datapath is proposed to save the area since the same set of processing elements (PE) is reused for different operations of GE.  ...  Chien for providing the core area information of the chip in [32] .  ... 
doi:10.1109/tcsi.2011.2123430 fatcat:fmjavf3a75cufpy4qtse4ujcgu
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