A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Filters
Complete activation scheme for FPGA-oriented IP cores design protection
2017
2017 27th International Conference on Field Programmable Logic and Applications (FPL)
Preserved Fulltext
We propose a hardware/software scheme which allows a designer to remotely activate an IP with minimal area overhead. The software modifies the IP efficiently and can handle very large netlists. ...
The protected IP is instantiated on the enrolled daughterboard. Before activation, the IP does not operate correctly. ...
the frame of the SALWARE project number ANR-13-JS03-0003 supported by the French "Agence Nationale de la Recherche" and by the French "Fondation de Recherche pour l'Aéronautique et l'Espace", funding for ...
doi:10.23919/fpl.2017.8056772
dblp:conf/fpl/ColombierMLPBF17
fatcat:rdhxug3ci5c2ndrjks4k7drjdi
Hardware Activation by Means of PUFs and Elliptic Curve Cryptography in Field-Programmable Devices
2016
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Reusable design using IP cores requires of efficient methods for protecting the Intellectual Property of the designer and the corresponding license agreements. ...
This secure channel allows the IP core vendor to send a unique Activation Code to the core in order to switch it to the Activated Mode, thus enabling all its features. ...
Parrilla is the author of the ideas and designs corresponding to the SEHAS protection system. E. ...
doi:10.3390/electronics5010005
fatcat:ez3m74kcdvgexce6evo7sho34m
PUF-based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment
2019
IEEE Access
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
To protect software IP, IP core vendor inserts copyright information and anonymous buyer identity information into the design before trading. ...
As an ideal hardware solution, field programmable gate array (FPGA) becomes a mainstream technology to design a complex system. The designed modules are named as intellectual property (IP) cores. ...
Therefore, an IP core is binding to a specific FPGA device. This scheme assumes system integration vendor is completely trustable. All CRPs of PUF in FPGA are stored by the system integration vendor. ...
doi:10.1109/access.2019.2925106
fatcat:kdn643u5pjd2hlxbl67yeuxiae
Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing
2013
2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We propose a new information assurance model which can dynamically track the information flow in circuit designs and hence protect sensitive data from malicious leakage. ...
The proposed cycle accurate information assurance scheme is successfully demonstrated on cryptographic circuits with various complexities from a small-scale DES encryption core to a state-ofthe-art AES ...
The increasing reliance on third-party IP cores for hierarchical designs makes it more important to protect IP cores against RTL Trojans. ...
doi:10.1109/hst.2013.6581573
dblp:conf/host/JinYM13
fatcat:2qdaa3yb5ng63o6jhqdqhs5mku
Analysis and design of active IC metering schemes
2009
2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Outsourcing the fabrication of semiconductor devices to merchant foundries raises some issues concerning the IP protection of the design. ...
Active hardware metering schemes try to counter piracy of integrated circuits by enforcing the fabrication plant to run an activation protocol with the IP owner for every chip that is produced. ...
ACKNOWLEDGMENTS This work was in part supported by the IAP Program P6/26 BCRYPT of the Belgian State, by K.U.Leuven-BOF funding (OT/06/04), by the FWO project G.0300.07 (Security components for trusted ...
doi:10.1109/hst.2009.5224964
dblp:conf/host/MaesSTV09
fatcat:ztobilkk2jaczb6lnra4h35hb4
Design and implementation of an industrial vector-controlled induction motor drive
2017
Sadhana (Bangalore)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Various monitoring and protection functions for the drive are implemented using a Cyclone IV FPGA that communicates with the DSC, and acts as the master controller for the drive. ...
This paper describes the implementation of a complete industrial vectorcontrolled drive for a 30 kW induction motor. ...
The FPGA side configuration showing the NIOS core along with connected IP cores and block diagram logic is shown in figure 4 . ...
doi:10.1007/s12046-017-0660-6
fatcat:jabcvlecv5bddouvv3hc7v3fny
On the Power of Optical Contactless Probing
2017
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security - CCS '17
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We demonstrate that the adversary is able to extract the plaintext data containing sensitive design information and intellectual property (IP). ...
To this end, we conduct an optical probing attack against the bitstream encryption feature of a common FPGA. ...
An additional advantage of this protection scheme is that it can also be employed by FPGA users on the reconfigurable logic without the need for hardware modifications. ...
doi:10.1145/3133956.3134039
dblp:conf/ccs/TajikLSB17
fatcat:dhzonae3ongybelyiostl56fna
Security of Cloud FPGAs: A Survey
[article]
2020
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
However, since the cloud FPGA technology is still in its infancy, the security implications of this integration of FPGAs in the cloud are not clear. ...
In this paper, we survey the emerging field of cloud FPGA security, providing a comprehensive overview of the security issues related to cloud FPGAs, and highlighting future challenges in this research ...
These are indicated in the figure by devil icons in the shell (PCIe module and IP core), user 1's logic, 3rd party IP core, and the FPGA design flow, respectively. ...
arXiv:2005.04867v1
fatcat:yr2habmipvfnbn64yvczvapi34
SoK: On the Security Challenges and Risks of Multi-Tenant FPGAs in the Cloud
[article]
2020
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Other Versions
We conclude with our insights and a call for future research to tackle these challenges. ...
This is enabled by leveraging the partial reconfiguration property of FPGAs, which allows to split the FPGA fabric into several logically isolated regions and reconfigure the functionality of each region ...
These built-in crypto cores are not exclusive for bitstream protection; they can be used by the users in their designs as well. ...
arXiv:2009.13914v2
fatcat:mbdpjfuoljderjhopoppxkxkoe
ECC Memory for Fault Tolerant RISC-V Processors
[chapter]
2020
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. ...
Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. ...
Hereby the newly created ECCmem component goes beyond existing IP such as Synopsis Design-Ware STAR ECC IP, the ARM Artisan embedded memory IP, and Xilinx ECC IP [14] . ...
doi:10.1007/978-3-030-52794-5_4
fatcat:el2loaxezzc3dkqiz5lh6a2w2e
Encryption AXI Transaction Core for Enhanced FPGA Security
2022
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
The core prevents unauthorized data extraction by encrypting data on the fly. ...
The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. ...
Firewall IP cores have been developed to protect the SoC from malicious software [30] . This passive security is achieved by active built-in security measures. ...
doi:10.3390/electronics11203361
fatcat:vb6v6fopv5bmbl7rvp6g2e26jm
FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
2021
Qubahan Academic Journal
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. ...
Since FPGAs can be defined as just one mission, computers are superior to them. ...
The paper also examined the hardware architecture for the efficient implementation of the proposed FPGA cipher core of the RC6-Cascade stack. ...
doi:10.48161/qaj.v1n2a38
fatcat:5sibubug4nhdzlp7on7ujvupta
PIL testing of the Optical On-board Image Processing Solution for EO-ALERT
2021
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Once the platform is ready, the new tools for programming Xilinx® COTS allow using all board resources such as IP cores in the FPGA for hardware acceleration or the use of parallel processing frameworks ...
(4 A53 ARM® cores) or FPGA. ...
We thank and acknowledge our partners DLR, OHB Italy, POLITO, TU-GRAZ, DEIMOS Imaging, for their collaboration and effort to achieve the project objectives. ...
doi:10.5281/zenodo.5575574
fatcat:dz3ceasnqfa23j3xqxm523dzsu
Dynamically configurable security for SRAM FPGA bitstreams
2006
International Journal of Embedded Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
FPGAs are becoming increasingly attractive -thanks to the improvement of their capacities and their performances. Today, FPGAs represent an efficient design solution for numerous systems. ...
His researches are in reconfigurable computing and particularly design space exploration for coarse-grained reconfigurable architecture. ...
This work was supported in part by the French Ministry for Education and Research. ...
doi:10.1504/ijes.2006.010166
fatcat:s3xphvilkvbmhezlioklcxdlsa
FPGA-based module for SURF extraction
2014
Machine Vision and Applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. ...
We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm's most computationally expensive process, the interest point detection. ...
If the user would wish to change these, he would need to modify the FPGA design only on the system level withouth altering the IP cores. ...
doi:10.1007/s00138-014-0599-0
fatcat:dj3ddob3xjeuroamg67olae46q
« Previous
Showing results 1 — 15 out of 1,430 results