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A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. ...
The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. ...
His research focuses on the areas of ASIC architectures for logarithmic-based processing, parallel computing architectures and LDPC codes. ...
doi:10.1109/tcsi.2009.2016592
fatcat:x7bzipwcijcr7b7vlgti5ywlte
Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed
2013
IEEE 2013 Tencon - Spring
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This paper presents the design, implementation, experimental verification, and validation of the proposed LDPC decoder using a real-time FPGA based baseband test. ...
Understanding its performance in the design and implementation of forward error correction codes in a realtime manner is necessary for rapid prototyping in research areas that are primarily based on emulation ...
ACKNOWLEDGMENT The authors would like to express gratitude towards the Sirindhorn International Thai-German Graduate School of Engineering (TGGS), Bangkok, Thailand for their equipment supports. ...
doi:10.1109/tenconspring.2013.6584426
fatcat:imicyevk2nfyfjtsi53fy2qpdu
FPGA-Oriented LDPC Decoder for Cyber-Physical Systems
2020
Mathematics
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In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. ...
Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems. ...
Funding: The study was partially supported by the Polish Ministry of Science and Higher Education.
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/math8050723
fatcat:x2ojjp6zdraa5ngl75fnlsq52u
High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes
2019
Periodica Polytechnica Electrical Engineering and Computer Science
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Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. ...
These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ...
As PG is a point-to-point interconnect with high node degrees, Bus Architecture is not suitable for our implementation. ...
doi:10.3311/ppee.14807
fatcat:xdsynkzhd5ea5flywmj65yr37a
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
2008
2008 16th International Symposium on Field-Programmable Custom Computing Machines
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We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. ...
It has been validated through an implementation on a Xilinx Virtex5 FPGA component. ...
For each code ratio of the WiMax LDPC standard [3] , the table gives, for a given number of modules, an optimal solution in terms of CN set quantity per module, bus quantity of the interconnection structure ...
doi:10.1109/fccm.2008.13
dblp:conf/fccm/CharotWFH08
fatcat:e2hf4mott5c2zabk4htmnnemai
Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes
2017
Tsinghua Science and Technology
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Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. ...
The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block ...
We also introduced a technique, called the cycle bus, to reduce the number of block RAMs in the multicore architecture, based on the classification of the multi-core architecture as either cooperative ...
doi:10.1109/tst.2017.7830899
fatcat:4vcttut6zvebfitrt7uczbyutq
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
2006
Signal Processing Systems Design and Implementation (siPS), IEEE Workshop on
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FPGA implementation of our proposed architectures for a (1536, 768) (3, 6)-regular QC LDPC code can achieve an estimated 61 Mbps decoding throughput at SNR= 4.5 dB. ...
In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. ...
FPGA IMPLEMENTATION RESULTS We implement five different partly parallel OSP decoder architectures proposed above -one based on the MS algorithm and four based on the balanced SP algorithm (using ψ(x)) ...
doi:10.1109/sips.2006.352585
dblp:conf/sips/ChenDY06
fatcat:a5o2zvzp4zcydenzy4zlbr64lu
A low complexity LDPC-BCH concatenated decoder for NAND flash memory
2018
IEICE Electronics Express
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Compared to the standalone LDPC decoder, the concatenated decoder only consumes 7% extra hardware and the code rate penalty is less than 1%. ...
The major challenge is the error floor problem. Dispersed array LDPC (DA-LDPC) code is highly structured and provides implementation convenience due to its regularity. ...
Fig. 4 4 shows the decoding architecture of the DA-LDPC code and the data width is marked on each bus. ...
doi:10.1587/elex.15.20180103
fatcat:4rajlcsqszchbkg7h3fxw3xv7i
Low Power QC-LDPC Decoder Based on Token Ring Architecture
2020
Energies
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The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature. ...
We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder ...
Implementation of the QC-LDPC Decoder Based on the Token Ring Architecture with Clock Gating It has been assumed that in the designed implementation of a decoder with an architecture based on Token Ring ...
doi:10.3390/en13236310
fatcat:d2sdtq7usjdylm5actmoncphby
An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform with QC-LDPC Codes
2021
IEEE Access
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This paper proposes a conventional iris authentication system and a hardware-friendly QC-LDPC error correction code scheme on a microprocessor-FPGA platform. ...
With the emergence and popularity of iris biometrics, there are increasing concerns regarding the feasibility of iris authentication systems and their corresponding variability reduction methods. ...
The QC-LDPC decoders were implemented on the FPGA section in Fig. 1 . ...
doi:10.1109/access.2021.3133908
fatcat:qjw7es2muncjndb5hr7e7p6ymq
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture
2007
2007 IEEE International SOC Conference
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Out of the decoding algorithms, the modified Min-Sum SPA is selected for implementation and optimization on a reconfigurable instruction cell architecture. ...
This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algorithms. ...
OPTIMIZATION ON THE RECONFIGURABLE ARCHITECTURE (RA) The simulation results for the un-optimized 'C' code on the RA are presented below: The straightforward implementation of decoder on the RA proved to ...
doi:10.1109/socc.2007.4545443
dblp:conf/socc/KhanAEKNMY07
fatcat:cnmxtrnjanavximjat6q43oeqa
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
2011
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. ...
Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 ...
We propose two architectural techniques to increase the throughput of an FPGA-based implementation of a LDPC decoder. ...
doi:10.1109/tcsi.2010.2055250
fatcat:2zc7gaotrrdlhl37ul52mp3bhi
DESIGN OF AN AREA-EFFICIENT HIGH-THROUGHPUT SHIFT-BASED LDPC DECODER
2013
Journal of Circuits, Systems and Computers
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An area-e±cient high-throughput shift-based LDPC decoder architecture is proposed. ...
An implementation of the proposed decoder using TSMC 0.18 m CMOS process achieves a decoding throughput of 1.725 Gbps, at a clock frequency of 56 MHz, a supply voltage of 1.8 V, and a core area of 5.18 ...
Based on the above analyzes, the proposed architecture is area-e±cient and power-e±cient. It can decode more data in terms of unit area and unit energy. ...
doi:10.1142/s0218126613500394
fatcat:a7pjpdcdzfaejmcynlvvxvfpfi
A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture
[article]
2011
arXiv
pre-print
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Supporting multiple heterogeneous LDPC codes on a parallel decoder poses serious problems in the design of the interconnect structure for such PEs. ...
The aim of this work is to explore the feasibility of NoC (Network on Chip) based decoders, where full flexibility in terms of supported LDPC codes is obtained resorting to an NoC to connect PEs. ...
In the n×n NoC based decoder, the upload is performed by means of n parallel buses, one for each row of the NoC ( Figure 5 ). Every bus sequentially updates the n nodes of a row. ...
arXiv:1105.2624v1
fatcat:2agbmcnfnngsln2mmb5e4nufui
An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes
[article]
2021
arXiv
pre-print
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We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. ...
Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. ...
Being one of the most crucial module, an implementable LDPC decoder should be considered, especially for embedded devices. ...
arXiv:2107.03688v1
fatcat:qobnq7v2dvd4dmjmztoalyte4u
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