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Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
2002
Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02
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Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. ...
In this paper, we address this problem and present: (1) a dynamic scheduler hardware architecture, and (2) four dynamic run-time scheduling algorithms for DRL-based multi-context platforms. ...
It is a heterogeneous architecture, which comprises a software processor, a DRL-based hardware architecture and shared memory resources. ...
doi:10.1145/774789.774831
dblp:conf/codes/NogueraB02
fatcat:yhzbxbulxba5zfu2zyljnfh4am
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
2002
Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02
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Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. ...
In this paper, we address this problem and present: (1) a dynamic scheduler hardware architecture, and (2) four dynamic run-time scheduling algorithms for DRL-based multi-context platforms. ...
It is a heterogeneous architecture, which comprises a software processor, a DRL-based hardware architecture and shared memory resources. ...
doi:10.1145/774827.774831
fatcat:5c6k7gof7fcq7d34qkldpn46ja
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627)
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Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. ...
In this paper, we address this problem and present: (1) a dynamic scheduler hardware architecture, and (2) four dynamic run-time scheduling algorithms for DRL-based multi-context platforms. ...
It is a heterogeneous architecture, which comprises a software processor, a DRL-based hardware architecture and shared memory resources. ...
doi:10.1109/codes.2002.1003626
fatcat:cdzm6kxtvbgbxgkahsdgbb2yru
Reconfigurable Computing and Hardware/Software Codesign
2008
EURASIP Journal on Embedded Systems
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The special issue on "Reconfigurable Computing and Hardware/Software Codesign" addresses the advances in reconfigurable computing architectures, in algorithm implementation methods, and in automatic mapping ...
The paper "Software-controlled dynamically swappable hardware design in partially reconfigurable systems," by C. Huang and H. ...
The special issue on "Reconfigurable Computing and Hardware/Software Codesign" addresses the advances in reconfigurable computing architectures, in algorithm implementation methods, and in automatic mapping ...
doi:10.1155/2008/731830
fatcat:f6r6tzbprzbcnouvjlsjakx5vm
A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer
[chapter]
2003
Lecture Notes in Computer Science
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This paper presents a codesign environment for the Ultra-SONIC reconfigurable computing platform which is designed specifically for real-time video applications. ...
A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our system is demonstrated with an FFT application. ...
Consequentially, neither system is suitable for hardware/software codesign. In this work, tasks can interchangeably be implemented in software or reconfigurable hardware resources. ...
doi:10.1007/978-3-540-45234-8_39
fatcat:b5xzc4doujd6pinbmso3g5cxgi
Codesign Methodology based FPGA and Embedded Linux for Motor Control
2018
Indonesian Journal of Electrical Engineering and Computer Science
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To handle with this complexity, the use of reconfigurable hardware/software codesign methodology using digital platforms becomes necessary. ...
This paper presents hardware/software codesign methodology with flexible hardware devices and configurable graphical user interface: the hardware architecture is based on field-programmable gate array ...
In this paper, authors propose dynamically reconfigurable HW/SW codesign approach for DC motor control. ...
doi:10.11591/ijeecs.v9.i1.pp204-211
fatcat:x5z5dir2mfhyhhfmiytrrupm7e
From Reconfigurable Architectures to Self-Adaptive Autonomic Systems
2009
2009 International Conference on Computational Science and Engineering
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During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration ...
Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain. ...
The increasing prominence of reconfigurable devices within such systems requires HW/SW codesign for SoCs to address the trade-off between software execution and reconfigurable hardware acceleration. ...
doi:10.1109/cse.2009.490
dblp:conf/cse/Santambrogio09
fatcat:4hzazfoovvfsrbypjtvygqbndq
HW/SW codesign techniques for dynamically reconfigurable architectures
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. ...
However, no previous work has been carried out in order to define a HW/SW codesign methodology with dynamic scheduling for run-time reconfigurable architectures. ...
ACKNOWLEDGMENT The authors acknowledge the Department of Research and Development of Hewlett-Packard Inkjet Commercial Division, Barcelona, Spain, for its support in the preparation of his Ph.D. dissertation ...
doi:10.1109/tvlsi.2002.801575
fatcat:3ojhhmr27fgxzcuvvj2xwbmyf4
Java driven codesign and prototyping of networked embedded systems
1999
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99
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of such systems is implemented in software; flexibility or reconfigurability is added to the list of non-functional requirements. ...
JACOP is a codesign environment based on Java and supports specification, co-synthesis and prototyping of networked embedded systems. ...
The target hardware platform consists of dynamically reconfigurable FPGAs (DPGAs). ...
doi:10.1145/309847.310068
dblp:conf/dac/FleischmannBK99
fatcat:razgrecspre23hfrjzdxpdclxi
Hardware/software codesign: a systematic approach targeting data-intensive applications
2005
IEEE Signal Processing Magazine
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For example, swapping tasks between hardware and software can result in a totally new structure in the control circuit. ...
A hardware model is usually very different from those used in software. These distinctive views of hardware and software tasks can cause problems in the codesign process. ...
His research interests include theory and practice of customizing hardware and software for specific application domains, such as graphics and image processing, multimedia, and communications. ...
doi:10.1109/msp.2005.1425894
fatcat:yirzlrhinjepre7olkgcufkqdm
Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors
2002
Proceedings of the 15th international symposium on System Synthesis - ISSS '02
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This article describes a new approach to HW-SW codesign for complex embedded systems, using high-level programming languages. ...
The hardware extensions are implemented as simple coprocessors consisting of a reconfigurable datapath and a control memory. ...
However, most hardware-software codesign systems fail to adequately separate behavior from architecture. ...
doi:10.1145/581199.581255
fatcat:fljrbprlfbgp7eqk73ilmoxwve
Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors
2002
Proceedings of the 15th international symposium on System Synthesis - ISSS '02
Preserved Fulltext
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The file type is application/pdf.
This article describes a new approach to HW-SW codesign for complex embedded systems, using high-level programming languages. ...
The hardware extensions are implemented as simple coprocessors consisting of a reconfigurable datapath and a control memory. ...
However, most hardware-software codesign systems fail to adequately separate behavior from architecture. ...
doi:10.1145/581250.581255
fatcat:yosfnwdrkzfjnhfgstlzzifwxa
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
2009
International Journal of Reconfigurable Computing
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This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. ...
We experimented with a system employing two reconfigurators. This work also extends the ILP formulation for a HW/SW Codesign scenario. A heuristic scheduler for this extension has been developed too. ...
Napoleon is a reconfiguration-aware scheduler for 2D dynamically partially reconfigurable architectures. ...
doi:10.1155/2009/541067
fatcat:czdlmy67ybejlna64l577jt3qa
A hardware-software real-time operating system framework for SoCs
2002
IEEE Design & Test of Computers
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Platform-Based Design of SoCs 44 The δ framework for RTOS-SoC codesign helps designers simultaneously build a SoC or platform-ASIC architecture and a customized hardwaresoftware RTOS. ...
However, changing the SoC architecture and associated software can require significant re-porting or reconfiguration of the real-time operating system. ...
RTOSs for SoCs. This article introduces the δ hardware-software RTOS framework, a prototype hardware-software generation tool that aids in customized RTOS-SoC codesign. ...
doi:10.1109/mdt.2002.1047743
fatcat:cfr6xhfbljgjbmvbdp2nqaz35e
Vision for liquid architecture
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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In the liquid architecture project, we are exploring ways in which architectural flexibility can be exploited to improve the execution properties of individual applications. ...
experimentation in the hardware/software codesign space. ...
Third, the hardware design need not be fixed prior to software development. Hardware and software can be designed in tandem (i.e., hardware/software codesign). ...
doi:10.1109/ipdps.2006.1639583
dblp:conf/ipps/ChamberlainCFL06
fatcat:ep4ohctwqfg3lcpa3zlzyegd7i
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