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Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
2010
International Journal of Reconfigurable Computing
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The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. ...
FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. ...
Then, we explain how to best take advantage of dual-output programmable logic blocks. The experimental results we obtain against SCA are provided in Section 3. ...
doi:10.1155/2010/375245
fatcat:xaz6lcoubnhf3ctlx4hkc63kae
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
2013
International Journal of Reconfigurable Computing
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This programmable architecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between different styles of asynchronous implementations. ...
In order to illustrate the FPGA flexibility and security, a case study has been implemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic. ...
Acknowledgments The authors would like to thank Jean-Luc Danger, Sylvain Guilley, and Sumanta Chaudhuri, from Institut Télécom ParisTech for the fruitful discussions and the shared design of the FPGA. ...
doi:10.1155/2013/517947
fatcat:wlrcnr4zzrg7zmdpnwp2cdsfv4
Triple Rail Logic Robustness against DPA
2008
2008 International Conference on Reconfigurable Computing and FPGAs
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Within this context, the scope of this paper is to evaluate, on and for FPGA, the robustness of triple rail logic against power analyses. ...
More precisely, this paper aims at demonstrating that the basic concepts on which leans this logic are valid and may provide interesting design guidelines to obtain DPA (Differential Power Analysis) resistant ...
Of course, other secure dual rail logics might be more robust than the considered dual rail logics. ...
doi:10.1109/reconfig.2008.75
dblp:conf/reconfig/LomneOMTRSC08
fatcat:t3mh4zevtrextfpgyldm4xxdgm
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust ...
In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. ...
ACKNOWLEDGMENT This work was partially supported by The ANR -ICTER Project (French National Research Agency), The International "Secure Communicating Solutions" Cluster, and the CAPES/COFECUB (French-Brazilian ...
doi:10.1109/date.2009.5090744
dblp:conf/date/LomneMTRSC09
fatcat:tog5s5z3rvfrtfijokl4dy5h54
Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses
2009
Journal of Integrated Circuits and Systems
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In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. ...
Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential ...
Thus, we evaluate the dual rail logic from Figures 1(a) and (b). Of course, other secure dual rail logics might be more robust than the considered dual rail logic. ...
doi:10.29292/jics.v4i1.293
fatcat:tvvjbbewf5aflay2zxaz5qqobm
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis
2015
IET Information Security
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As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential ...
Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. ...
In this article, we aim to have verifications of the routing impact for a secure balanced cell-based dual-rail logic (BCDL) [13] implemented AES core with strict dual-rail networks. ...
doi:10.1049/iet-ifs.2013.0058
fatcat:5uxbn3t4ajb2rfperwauogjtti
An Asynchronous PLA with Improved Security Characteristics
2006
9th EUROMICRO Conference on Digital System Design (DSD'06)
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Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. ...
Finally, we demonstrate how our PLAs can be used as building blocks of large-scale systems with good security characteristics, when combined with special return-to-zero asynchronous latches. ...
Two recent works [3, 6] focused on dual-rail logic for security purposes, since by nature it tends to offer balanced power consumption and fault detection capabilities. ...
doi:10.1109/dsd.2006.22
dblp:conf/dsd/OikonomakosM06
fatcat:l47sflnfkrhp5ekw6ogvtbw6la
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
[article]
2011
arXiv
pre-print
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The logic block architecture is presented in detail. ...
This article presents an asynchronous FPGA architecture for implementing cryptographic algorithms secured against physical cryptanalysis. ...
LOGIC BLOCK ARCHITECTURE Fig. 6 (a) depicts the structure of the PLB (Programmable Logic Block) able to handle the main QDI asynchronous styles. ...
arXiv:1103.1360v2
fatcat:5bwt534f4jexlpxwamzfvltaiy
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
2022
Applied Sciences
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The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of mechanisms to achieve a higher level of security at minimum cost and with reasonable ...
In recent years, dozens of proposals have been presented to design circuits resistant to power analysis attacks. ...
Another alternative, to avoid the well-known early propagation effect, is balanced cell-based dual-rail Logic (BCDL) [30] . ...
doi:10.3390/app12052390
fatcat:cu2mactyevautgxmychwcuvqvy
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA
2012
22nd International Conference on Field Programmable Logic and Applications (FPL)
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The SCA resistance is based on dual-rail precharge logic. ...
The resulting countermeasure applies to a broad class of block ciphers. ...
Principle of Dual-rail Precharge Logic (DPL) The cause of side-channel leakage is data-dependent processing. ...
doi:10.1109/fpl.2012.6339236
dblp:conf/fpl/ManeTS12
fatcat:a57jwxf5vjaspb4fpylyl4ynjy
Power Side Channels in Security ICs: Hardware Countermeasures
[article]
2016
arXiv
pre-print
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The aim is to highlight exposed vulnerabilities in hardware-based countermeasures for future more secure implementations. ...
Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring the power consumption. ...
Inversion is inherent in a dual-rail logic gate by swapping the two outputs. ...
arXiv:1605.00681v1
fatcat:lwx5jvoh5nh2ziyr3ibuuctxdq
Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present
2021
Journal of Integrated Circuits and Systems
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In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. ...
Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. ...
The authors would like to thank PPGC and UFPel for support our research. R. Lellis would like to thank the IFSUL for his license to pursuing the Ph.D. ...
doi:10.29292/jics.v16i2.501
fatcat:y4zvlpnujrdchnjcmfm7ivif7m
Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem
2021
Journal of Low Power Electronics and Applications
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We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. ...
We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. ...
In dual-rail logic, the 6-bit secret-key is represented by 12-bit dual-rail signals, and the 5-bit base point value is represented by 10-bit dual-rail signals. ...
doi:10.3390/jlpea11040043
fatcat:witvcqbufjfrfellgkebmjgdqm
Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs
[chapter]
2015
Lecture Notes in Computer Science
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With respect to dual-rail logics most of these schemes have originally been designed for ASIC platforms, but much efforts have been spent to map them to FP-GAs as well. ...
In this work we show that this general technique -regardless of the underlying dual-rail logic -is incapable to properly prevent side-channel leakages. ...
[16] introduced Balanced Cell-based Dual-rail Logic (BCDL) that connects a global precharge signal with all gate inputs to a rendezvous box which is placed in front of each gate. ...
doi:10.1007/978-3-319-21476-4_6
fatcat:jwz2wsa7abgcfanlo233yf6si4
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
2008
2008 Second International Conference on Secure System Integration and Reliability Improvement
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We investigate "wave dynamic differential logic" (WDDL), a logic-level counter-measure based on leakage hiding thanks to balanced dual-rail logic. ...
An experimental security evaluation of the DES encryption algorithm in WDDL shows that the usage of positive logic is mandatory to resist to straightforward attacks. ...
On the other hand, secure blocks must pass through a more specific synthesis process. Power-constant dual-rail logic, as the DES data-and key-path, must be synthesized carefully. ...
doi:10.1109/ssiri.2008.31
dblp:conf/ssiri/GuilleySDGM08
fatcat:bcq4xepswvczdmlhliusljpj7i
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