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An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
2013
International Journal of Reconfigurable Computing
This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65 nm to target various styles of asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-ndata encoding. This programmable architecture is
doi:10.1155/2013/517947
fatcat:wlrcnr4zzrg7zmdpnwp2cdsfv4