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A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
[article]
2011
arXiv
pre-print
This article presents an asynchronous FPGA architecture for implementing cryptographic algorithms secured against physical cryptanalysis. We discuss the suitability of asynchronous reconfigurable architectures for such applications before proceeding to model the side channel and defining our objectives. The logic block architecture is presented in detail. We discuss several solutions for the interconnect architecture, and how these solutions can be ported to other flavours of interconnect (i.e.
arXiv:1103.1360v2
fatcat:5bwt534f4jexlpxwamzfvltaiy