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High-Level Verification
2009
IPSJ Transactions on System LSI Design Methodology
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In this paper, we present a survey of high-level verification techniques that are used for both verification and validation of high-level designs, that is, designs modeled using high-level programming ...
System-level design methods seek to combat this complexity by shifting increasing design burden to high-level languages such as SystemC and SystemVerilog. ...
Formal Assertions Narasimhan, et al. proposed a Formal Assertions approach 71)-73) to building a verified high-level synthesis system, called Asserta. ...
doi:10.2197/ipsjtsldm.2.131
fatcat:xb27xitplbgppig6z5galpr6ue
Formal synthesis in circuit design — A classification and survey
[chapter]
1996
Lecture Notes in Computer Science
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We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. ...
We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view. ...
Acknowledgements The authors are grateful to the anonymous referees whose constructive comments have improved the quality of the paper. ...
doi:10.1007/bfb0031817
fatcat:bz6cob6jd5bo3izawypciavotq
Formal methods for engineering special-purpose parallel systems introduction to minitrack
2003
36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the
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Hawkins emphasises the use of algebraic laws of functional programming to transform high-level specifications into Handel-C programs which, in turn, can be compiled into efficient circuits running on reconfigurable ...
The paper An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow by Dominique Borrione et. al. describes a method for asynchronous circuit design which includes automatic ...
Hawkins emphasises the use of algebraic laws of functional programming to transform high-level specifications into Handel-C programs which, in turn, can be compiled into efficient circuits running on reconfigurable ...
doi:10.1109/hicss.2003.1174807
fatcat:5ckhdatqzzh5tnysh7eeq6ieku
Transformational System Design Based on Formal Computational Model and Skeletons
[chapter]
2001
System-on-Chip Methodologies & Design Languages
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The Formal System Design methodology ForSyDe [1, 2, 3] is extended by a systematic refinement methodology based on transformations, which gradually transforms a high-level, function oriented system description ...
We illustrate the use of transformations with three examples taken from an ATM based network terminal system. ...
Introduction System level functional validation has been identified as one of the most severe obstacles to increased design productivity and quality. ...
doi:10.1007/978-1-4757-3281-8_15
fatcat:v34ycqmbr5cn5cgoofawm4i65e
Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment
2017
International Robotics & Automation Journal
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One serious problem of automated high-level synthesis tools is their inability of at least difficulty to use for low, bit level functions such as signal processing blocks. ...
Cubed-C is a full-strength high-level synthesis CAD system; nevertheless, its structure and properties make it particularly suitable for this type of fine-grained applications. ...
The methodology of System Co Designer [25] uses an actororiented approach so as to integrate HLS into electronic system level (ESL) design space exploration tools. ...
doi:10.15406/iratj.2017.02.00029
fatcat:7zpbc5ibfrgelgfiqfed33a3me
Verification method of dataflow algorithms in high-level synthesis
2007
Journal of Systems and Software
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This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow algorithms. ...
How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. ...
Conclusion This paper aims to exploit formal verification techniques for high-level synthesis. ...
doi:10.1016/j.jss.2006.12.547
fatcat:muuooxfxtbbflonrwngvbelmn4
From VHDL to efficient and first-time-right designs: a formal approach
1996
ACM Transactions on Design Automation of Electronic Systems
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In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. ...
As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. ...
ACKNOWLEDGMENTS The authors wish to thank their colleagues at IMEC (Z. Sahraoui ...
doi:10.1145/233539.233541
fatcat:yq72f3twtzeyxgwdmm7kbzkcyq
VERIFICATION OF DATAFLOW SCHEDULING
2008
International journal of software engineering and knowledge engineering
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However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. ...
This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-modelverifier (SMV) techniques. ...
Conclusion This paper aims to exploit formal verification techniques for high-level synthesis. ...
doi:10.1142/s0218194008003891
fatcat:xf2ytemtsbbu5morvvidjkqzvu
Formal Runtime Monitoring Approaches for Autonomous Vehicles
2020
Artificial Intelligence and fOrmal VERification, Logic, Automata, and sYnthesis
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The output of the controller is fed to the monitor (generated using formal runtime monitor synthesis approach), which enforces desired safety policies on the output of the system. ...
Formal verification techniques are needed for thorough verification and validation of such safety-critical systems. ...
of dynamic formal monitoring approaches in more complex settings. ...
dblp:conf/overlay/ShankarRPR20
fatcat:64rdemkenza6xfjpkmc4eepaza
A Case Study on Controller Synthesis for Data-Intensive Embedded Systems
2009
2009 International Conference on Embedded Software and Systems
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The resulting model is then transformed into a synchronous program from which a controller is synthesized by using a formal technique, in order to enforce the safe behavior of the modeled application while ...
The whole study is carried out in a design framework, GASPARD, dedicated to high-performance embedded systems. ...
Model-based approaches carry out the system design at a high level of abstraction, and the back-end model transformations enable to automatically generate implementation code. ...
doi:10.1109/icess.2009.12
dblp:conf/icess/GamatieYDR09
fatcat:6ipraialmzgtthzntc6pzxzhii
High-level Synthesis Integrated Verification
2015
Engineering, Technology & Applied Science Research
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In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. ...
Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. ...
A formal, rapid and integrated with synthesis, verification approach based on the Cubed-C High-level Synthesis system was discussed in this paper. ...
doi:10.48084/etasr.596
fatcat:ocbsn6gyyvb4fewihqp2qwus2i
Specification-based sketching with Sketch
2011
Proceedings of the 13th Workshop on Formal Techniues for Java-Like Programs - FTfJP '11
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We also recount our experience applying the tool to aid optimistic parallel execution frameworks, where we used it to discover and verify operation inverses, commutativity conditions, and operational transformations ...
In such a language, highlevel specifications in the form of pre-and postconditions annotate code, which can be formally verified using decision procedures. ...
Kim et al. recently used high-level specifications over abstract states of data structures to formally prove the correctness of operation inverses and commutativity conditions for a large number of data ...
doi:10.1145/2076674.2076677
dblp:conf/ecoop/SamimiR11
fatcat:d3taxp6465adhhpcjorpgoqelu
Are Hls Tools Healthy? The C-Cubed Project
2015
Zenodo
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High-Level Synthesis (HLS) plays a critical role in the required Electronic System Level (ESL) methodologies. ...
However, most of the available academic and commercial High-Level Synthesis (HLS) tools still do not play an established role in the system and hardware engineering teams. ...
scheduling phase [11] , a formal method for accurate high-level casting of optimal adders and subtractors [12] , and an exploration approach, called Spectral-aware Pareto Iterative Refinement, that ...
doi:10.5281/zenodo.16989
fatcat:fcirdvxuwvgjhd73eqcqr554f4
Functional Equivalence Verification Tools in High-Level Synthesis Flows
2009
IEEE Design & Test of Computers
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Once a high-level synthesizable description is obtained in this manner, it can automatically be transformed into an RTL description through appropriate high-level synthesis tools. ...
High-Level Synthesis Editor's note: High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification ...
Direct questions and comments about this article to Anmol Mathur, Calypto Design Systems, 2903 Bunker Hill Lane, Santa Clara, CA 95054; amathur@calypto.com. ...
doi:10.1109/mdt.2009.79
fatcat:jmkzzjmujndl5iexr2u4zeupyu
Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques
2013
Advances in Robotics & Automation
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Abstract The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). ...
These intelligent and formal techniques make the whole transformation from source code to implementation, formal. ...
These actors are used by the System Co-Designer [17] to exercise electronic system level (ESL) design space exploration. ...
doi:10.4172/2168-9695.1000121
fatcat:6vwlruh4yfg2bi6dhyhmz2uoy4
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