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Efficient parallel algorithms on restartable fail-stop processors
1991
Proceedings of the tenth annual ACM symposium on Principles of distributed computing - PODC '91
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We study efficient deterministic executions of parallel algorithms on restartable fail-stop CRCW PRAMs. ...
These results are based on a new algorithm for the Write-All problem "P processors write l's in an array of size N", together with a modification of the nain algorithm of [KS 89] and with the techniques ...
an earlier draft. algorithm X in the case of fail-stop errors without restarts? ...
doi:10.1145/112600.112603
dblp:conf/podc/KanellakisS91
fatcat:cvyk3523cvhodgp7hh76uojpci
Parallel Algorithms with Processor Failures and Delays
1996
Journal of Algorithms
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Acknowledgements: \\e would like to thank Jeff Vitter, larc Snir, and Naomi Nislilmura for helpful discussions, and Franco Preparata for reviewing an earlier draft of this paper.
REFPERENCES ...
Algorithm W of [KS 89] is an efficient fail-stop-(no-restart) Write-All solution. ...
In Section 4 we present three efficient algorithms for the Write-All problem. ...
doi:10.1006/jagm.1996.0003
fatcat:4wfmzybe5bbhlcxki6injrdcam
FAILURE-SENSITIVE ANALYSIS OF PARALLEL ALGORITHMS WITH CONTROLLED MEMORY ACCESS CONCURRENCY
2007
Parallel Processing Letters
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This result yields tighter bounds on work (vs. [16] ) for simulations of pram algorithms on fail-stop prams. ...
This paper considers determinitic solutions for the Write-All and iterative Write-All problems in the fail-stop synchronous crcw pram model where memory access concurrency needs to be controlled. ...
[16] ) for simulations of pram algorithms on fail-stop prams. ...
doi:10.1142/s0129626407002946
fatcat:ivgdpkgcprdmbcsy7imcdva3la
What is scalability?
1990
SIGARCH Computer Architecture News
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For this reason, current use of the term adds more to marketing potential than technical insight. ...
In this paper, I first examine formal definitions of scalability, but I fail to lind a useful, rigorous definition of it. ...
An nprocessor PRAM has a single globally-addressable memory and n processors that operate on a lock-step read-memory, compute, write-memory cycle. ...
doi:10.1145/121973.121975
fatcat:wl7xvnwnnfeb3bvaete6a3l5qu
Reliable computations on faulty EREW PRAM
1996
Theoretical Computer Science
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We also show an optimal safe algorithm for computing prefix sums, which works in time O(log n) on an O(n/ log n)-processor EREW PRAM. ...
We consider the problem of efficient and reliable computing on EREW PRAM whose processors are subject to random independent stop-failures with constant probability p < 1. ...
We assume that the action of writing to shared memory is atomic with respect to faults, i.e. a processor does not fail in the process of writing. ...
doi:10.1016/0304-3975(95)00186-7
fatcat:kmiwme5oebfl7bsdxxwfcjwgja
RePRAM: Re-cycling PRAM faulty blocks for extended lifetime
2012
IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)
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As main memory systems begin to face the scaling challenges from DRAM technology, future computer systems need to adapt to the emerging memory technologies like Phase-Change Memory (PCM or PRAM). ...
In this paper, we propose a novel PRAMbased main memory system, RePRAM (Recycling PRAM), which leverages a group of faulty pages and recycles them in a managed way to significantly extend the PRAM lifetime ...
This makes the Fail Stop scheme quickly decommission all of the pages within a short window of writes before the PCM's effective capacity drops to zero. ...
doi:10.1109/dsn.2012.6263950
dblp:conf/dsn/ChenVH12
fatcat:igo5kqhvxfdwralbnmmahpjnku
Deterministic Computations on a PRAM with Static Processor and Memory Faults
[article]
2018
arXiv
pre-print
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The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and a constant fraction of m memory cells. ...
We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. ...
The authors thank Krzysztof Diks for discussions of the related faulttolerance issues, and to Piotr Indyk for sharing his insights on the Discrete Fourier Transform and information dispersal. ...
arXiv:1801.00237v2
fatcat:3fbdp74vd5ebfd3okd6vytaxai
Total Eclipse - an Efficient Architectural Realization of the Parallel Random Access Machine
[chapter]
2010
Parallel and Distributed Computing
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initialized memory location triggers an external memory reference using the processor-wise multioperation result as an operand. ...
strong PRAM model on a physically distributed memory architecture (so called PRAM mode) and an efficient NUMA model for low TLP locality-optimized code (so called NUMA mode) (Forsell, 2009 ). ...
PRAM mode and to an ALU subinstruction, a memory subinstruction, a sequencer subinstruction, and two write back subinstructions in the NUMA mode. ...
doi:10.5772/9446
fatcat:xc6rf24okjcdzodaia72aey7ky
Cooperative asynchronous update of shared memory
2005
Proceedings of the thirty-seventh annual ACM symposium on Theory of computing - STOC '05
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The Write-All problem for an asynchronous shared-memory system has the objective for the processes to update the contents of a set of shared registers, while minimizing the total number of read and write ...
The most efficient previously known deterministic algorithm performs O(n 1+ε ) reads and writes, for an arbitrary fixed constant ε > 0, and is due to Anderson and Woll [4]. ...
One could argue that this is the case by pointing that repeating a pattern of memory accesses for reading, in an execution of an algorithm solving Collect, as a pattern of memory accesses for writing, ...
doi:10.1145/1060590.1060698
dblp:conf/stoc/ChlebusK05
fatcat:b6r4o2r2kzfzpep23im77uei6a
Security refresh
2010
SIGARCH Computer Architecture News
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Phase-change Random Access Memory (PRAM) is an emerging memory technology for future computing systems. ...
Furthermore, all of these prior techniques failed to consider the circumstances when a compromised OS is present and its security implication to the overall PRAM design. ...
From Figure 6 (a) to (e), we start from an initial state with eight successive security refreshes for eight memory blocks in one PRAM region. ...
doi:10.1145/1816038.1816014
fatcat:sny5vypkqnb7je27awv5ujpkee
Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks
2014
ACM Journal on Emerging Technologies in Computing Systems
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DRAM technology challenges have increased the necessity to adapt to the emerging memory technologies like Phase-Change Memory (PCM or PRAM). ...
In this article, we explore a novel PRAM-based main memory system which resuscitates a group of faulty pages in a cost-effective manner to significantly extend the PCM main memory lifetime while minimizing ...
This makes the Fail Stop scheme quickly decommission all of the pages within a short window of writes before the PCM's effective capacity drops to zero. ...
doi:10.1145/2602156
fatcat:fxt4k6fccvgs5p6zopxy66aequ
Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness
2018
Journal of Cryptology
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Oblivious RAM (ORAM) is a cryptographic primitive that allows a trusted CPU to securely access untrusted memory, such that the access patterns reveal nothing about sensitive data. ...
ORAM is known to have broad applications in secure processor design and secure multi-party computation for big data. ...
We define a new model for oblivious execution of programs, where an adversary cannot observe the memory offset within each memory bank, but can observe the patterns of communication between the CPU(s) ...
doi:10.1007/s00145-018-9301-4
fatcat:4uu32x765jhafnvyvibflmbgbq
A wait-free sorting algorithm
1997
Proceedings of the sixteenth annual ACM symposium on Principles of distributed computing - PODC '97
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In this paper we present the first wait-free algorithm for sorting an input array of size N using P s N proceseom to achieve optimal running time. ...
The randomized algorithm we present here, when run in the CRCW PRAM model executes in optimal O(log N) time where P = N and O(N log N/P) otherwise. ...
To fill the fat tree with values we will use an approximation of the write-all problem, write-most. ...
doi:10.1145/259380.259432
dblp:conf/podc/ShavitUZ97
fatcat:yn5x2vmsibcyhfvl2cotq5ukuq
Algorithm Engineering for Parallel Computation
[chapter]
2002
Lecture Notes in Computer Science
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The emerging discipline of algorithm engineering has primarily focused on transforming pencil-and-paper sequential algorithms into robust, efficient, well tested, and easily used implementations. ...
As parallel computing becomes ubiquitous, we need to extend algorithm engineering techniques to parallel computation. Such an extension adds significant complications. ...
Algorithms for SMPs While an SMP is a shared-memory architecture, it is by no means the PRAM used in theoretical work. ...
doi:10.1007/3-540-36383-1_1
fatcat:m6ayomzqk5flzkl2blp7x5cvji
Efficient execution of nondeterministic parallel programs on asynchronous systems
1996
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures - SPAA '96
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We seek an automatic execution scheme, which allows the asynchronous system to execute the synchronous program. ...
Total work is defined to be the summation of the number of steps performed by all processors (including steps from busy waiting). ] 1997 Academic Press article no. IC972653 1 0890-5401Â97 25.00 ...
Kannellakis and Shvartman [18, 19] introduce the fail-stop PRAM model and describe solutions to specific algorithmic problems in this model. ...
doi:10.1145/237502.237566
dblp:conf/spaa/AumannBZ96
fatcat:4ppcjnjclbbjrf5spuak5jubfq
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