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Power Supply Noise in Delay Testing
2006
Test Conference (ITC), Proceedings, IEEE International
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Walker As technology scales into the Deep Sub-Micron (DSM) regime, circuit designs have become more and more sensitive to power supply noise. Excessive noise can significantly ...
For static compaction and test fill purposes, however, the entire test sets generated by CodGen were used. ...
using the compacted test set, which is generated from the previous uncompacted test set using static compaction. ...
doi:10.1109/test.2006.297642
dblp:conf/itc/WangWMKGVWE06
fatcat:kkmafdsw5reznblofwrdr42xw4
Low-power scan testing and test data compression for system-on-a-chip
2002
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Since static compaction of scan vectors invariably leads to higher power for scan testing, the conflicting goals of low-power scan testing and reduced test data volume appear to be irreconcilable. ...
Experimental results for the larger ISCAS 89 benchmarks show that reduced test data volume and low power scan testing can indeed be achieved in all cases. ...
We also thank Rafael Medina for helping us in our experiments with the IBM test data. ...
doi:10.1109/43.998630
fatcat:36ogvlyysjf4hcohqpgsxo7cme
Implementation of Low Power Circuit Analysis with Applications of Test Vectors
2015
IJIREEICE
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The main purpose of having intermediate patterns is to minimize the transitional processing at initial inputs; this could minimize the switching activities at circuit under test. ...
This could perform fault analysis and also minimize the power utilization at circuit level during tests, by generating three intermediate patterns between random patterns by decreasing the hardware components ...
Carefully selecting the merging order of test cube pairs during static compaction reduces both average and peak power for the final conventional static compaction techniques that randomly merge test cubes ...
doi:10.17148/ijireeice.2015.31235
fatcat:h7bzcza2hjhjtmdxbfdzbygdd4
A Comparative Study of Low Power Testing Techniques for Digital Circuits
2017
International Journal of Advanced Research in Computer Science and Software Engineering
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process the power consumed is much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing. ...
In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. ...
The low correspondence among test vectors raise switching activity and ultimately leads to power dissipation in the circuit. ...
doi:10.23956/ijarcsse/v7i7/0180
fatcat:hiimyltyuzhuxoz3fv7qhgfgte
Thermal characterization of BIST, scan design and sequential test methodologies
2009
2009 International Test Conference
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Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. ...
Results also demonstrate that low power testing techniques are not necessarily temperature-aware. ...
Dick and David Bild of University of Michigan for useful feedback. This work was supported by SRC under contract no. 2007-TJ-1589. ...
doi:10.1109/test.2009.5355733
dblp:conf/itc/SimsirJ09
fatcat:b63qlfvezjhznb3wqy2idqxfxi
Survey of low-power testing of VLSI circuits
2002
IEEE Design & Test of Computers
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Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design. ...
SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. ...
Pravossoudovitch for working with me in the field of low-power testing. I also thank the reviewers and editors for their suggestions and constructive criticism. ...
doi:10.1109/mdt.2002.1003802
fatcat:fktqa7fywfca5bjmonw44huaqe
Low Power Estimation on Test Compression Technique for SoC based Design
2015
Indian Journal of Science and Technology
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This paper analyzes the test power consumption for the test data to get the low power consumption by using switching activity. ...
The Low Power Transition -X filling (LPT-X) method is proposed to reduce the transition switching where unknown bits were filled. ...
Test set compaction is generated by Mintest 17 by full scanned ISCAS89 bench mark circuits. The paper 18 shows the various power consumption methods to achieve low power under testing. ...
doi:10.17485/ijst/2015/v8i14/61848
fatcat:m3zbk7v6m5clrbkave3rlybyqu
On Power-profiling and Pattern Generation for Power-safe Scan Tests
2007
2007 Design, Automation & Test in Europe Conference & Exhibition
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With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. ...
The proposed technique also comprehends irregular power grid topologies for constraints on localized switching activity. ...
For the worst-case, the overall pattern count increased by 7.7% for s38417, while for the best case, the overall pattern count reduced by 2.3% for c1355. ...
doi:10.1109/date.2007.364648
dblp:conf/date/DevanathanRK07
fatcat:djrnwsxklzgyxdvasgmvp6yt4m
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
2007
European Test Symposium
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Then we propose a power evaluation framework based on a combination of tools from the testing and computer architecture technical areas. ...
a low energy perspective. ...
The importance of static power consumption increases as dimensions scale down, however current CMOS technologies are dominated by dynamic power consumption. ...
doi:10.1109/ets.2007.36
dblp:conf/ets/MerentitisKPG07
fatcat:qmzm7uroovacxmu7ngemc3sfx4
Survey of Low Power Testing of VLSI Circuits
2013
Science Journal of Circuits Systems and Signal Processing
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This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques. ...
The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. ...
Thus, low power test vector compaction techniques have been introduced to minimize the number of test cubes generated by the ATPG tool by merging test cubes that are compatibles in all bit positions under ...
doi:10.11648/j.cssp.20130202.15
fatcat:bqr2cde4hndmznp52ajg4rlyku
Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review
2015
IJIREEICE
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A new low power test pattern generator using linear feedback shift register (LFSR), called LP-TPG, and is presented to reduce the average power and peak power of the circuit by reducing the switching activities ...
From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage. ...
Four reasons are blamed for power increase during test. High switching activity due to nature of test patterns Parallel activation of internal cores during test Power consumed by extra design-for-test ...
doi:10.17148/ijireeice.2015.3429
fatcat:36upg5ss4rfwvltaxo4cgvo2xa
Survey of low power testing of VLSI circuits
2012
2012 International Conference on Computer Communication and Informatics
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This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques. ...
The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. ...
Thus, low power test vector compaction techniques have been introduced to minimize the number of test cubes generated by the ATPG tool by merging test cubes that are compatibles in all bit positions under ...
doi:10.1109/iccci.2012.6158884
fatcat:7lxdohsoivfsrnqsaese2j5uvm
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme
2003
IEEE Journal of Solid-State Circuits
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The proposed TCAM cell uses 4T static storage for increased density. ...
The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. ...
Roth for the initial idea of the cell, P. Gillingham and D. Perry for the initial idea of match-line sensing scheme, and R. Colbeck and T. Wojcicki for their encouragement and support. ...
doi:10.1109/jssc.2002.806264
fatcat:4tvu5swhp5bxlm4y2ifqojstky
A static‐commutated device to contain voltage variations for low‐voltage active users
2021
IET electric power applications
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Variations of active power injections/absorptions by active users can produce longduration variations of the voltage amplitudes that exceed normal operating ranges admitted for the feeders, thus causing ...
The ever-wider spread of distributed generation in distribution systems feeds the increasing demand for voltage regulation in low-voltage networks. ...
The regulation is operated by automatically stepping among multiple tap settings, thanks to a voltage regulator that sets the adequate voltage for the downstream lines. ...
doi:10.1049/elp2.12090
fatcat:csg5cr5sizdgzn54vjpm2bjeei
Development of Simulink Based Modeling Platform for 3.3kV/400A SiC MOSFET Power Module
2018
2018 IEEE Energy Conversion Congress and Exposition (ECCE)
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The developed model has been validated with the experimental data both for static and dynamic tests at several temperatures. ...
The main objective of this paper is to develop a Simulink based modeling platform for a commercial 3.3 kV/400 A SiC MOSEFT power module. ...
The efficiency of the converter is mainly defined by the high diode losses, whereas both the conduction and the switching losses of the model are low, as expected. ...
doi:10.1109/ecce.2018.8557772
fatcat:lr2r5gujevckjpturgre7ipfyu
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