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Hardware-software partitioning and pipelined scheduling of transformative applications
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We present a tool for hardware-software partitioning and pipelined scheduling of transformative applications. ...
The performance of embedded hardware-software systems that implement transformative applications can be maximized by obtaining a pipelined design. ...
This paper presents a tool for HW-SW partitioning and pipelined scheduling of transformative applications.
A. ...
doi:10.1109/tvlsi.2002.1043323
fatcat:5piedlpp6vgv3jvfhdjkl7cbfi
Codesign of embedded systems: status and trends
1998
IEEE Design & Test of Computers
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supported at different levels of abstraction. s The intermediate results of process transformation and hardware-software partitioning and scheduling can be used for the final design, and therefore, there ...
Figure 5 shows that the system architecture development process of Figure 1 has been detailed into the process transformation, hardware-software partitioning, and scheduling steps. ...
doi:10.1109/54.679207
fatcat:7ghyeusfczbepg5adsbge3qvhu
A Parallel Loop Scheduling Scheme on Field Programmable Gate Arrays
2016
Innovative Computing Information and Control Express Letters, Part B: Applications
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The designers in reconfigurable computing fields always require considerable knowledge in both software and hardware to build hybrid applications. ...
The modulo scheduling schemes with a constant initiation interval in most compilers schedule the iterations and generate pipelines by using a pipeline division method. ...
The applications should be partitioned to software and hardware parts. The software programs run in the general purpose processors such as CPUs. ...
doi:10.24507/icicelb.07.02.363
fatcat:e55ljhrxwjgmre2eiykuo2djvq
Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design
2005
ETRI Journal
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We developed a pipelined scheduling technique of functional hardware and software modules for platformbased system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. ...
We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. ...
Pipelined Hardware and Software Scheduling Transformative applications are dominated by dataflow operations with few control-flow operations. ...
doi:10.4218/etrij.05.0905.0011
fatcat:5vuh2zd2rzejpmiaak3qjd3qdi
Pipeline vectorization
2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents pipeline vectorization, a method for synthesizing hardware pipelines based on software vectorizing compilers. ...
The method improves efficiency and ease of development of hardware designs, particularly for users with little electronics design experience. ...
Partitioning and Integration The last pipeline vectorization phase performs hardware-software partitioning as well as hardware integration. 1) Hardware-Software Partitioning: Partitioning determines which ...
doi:10.1109/43.908452
fatcat:na5hmfvndra3hnywt75lpih7qu
Compilers for instruction-level parallelism
1997
Computer
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Such a partitioning sim-plifies the hardware. (For a short discussion of hardware architectures, see the "Architectures and ILP" sidebar.) ...
These compilers use trace scheduling or software pipelining to accelerate a broad class of loops with greater efficiency than earlier vector processors. 3,4 ...
To alleviate this problem, an ILP compiler must provide a software architecture that partitions applications into regions of manageable size. ...
doi:10.1109/2.642817
fatcat:sqa3irdg3zcqzftmok3rpsv65a
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
2006
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII
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As benchmarks exhibit different amounts of task, data, and pipeline parallelism, we exploit all types of parallelism in a unified manner in order to achieve this generality. ...
In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. ...
Acknowledgments We would like thank the members of the StreamIt team, both past and present, and especially Jasper Lin, Rodric Rabbah, and Allyn Dimock for their contributions to this work. ...
doi:10.1145/1168857.1168877
dblp:conf/asplos/GordonTA06
fatcat:z6oxfi2pizamdircj2pkckqn7m
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
2006
SIGARCH Computer Architecture News
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As benchmarks exhibit different amounts of task, data, and pipeline parallelism, we exploit all types of parallelism in a unified manner in order to achieve this generality. ...
In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. ...
Acknowledgments We would like thank the members of the StreamIt team, both past and present, and especially Jasper Lin, Rodric Rabbah, and Allyn Dimock for their contributions to this work. ...
doi:10.1145/1168919.1168877
fatcat:ha2w3gf64vg3bfhmsbu4y64zdi
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
2006
ACM SIGOPS Operating Systems Review
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As benchmarks exhibit different amounts of task, data, and pipeline parallelism, we exploit all types of parallelism in a unified manner in order to achieve this generality. ...
In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. ...
Acknowledgments We would like thank the members of the StreamIt team, both past and present, and especially Jasper Lin, Rodric Rabbah, and Allyn Dimock for their contributions to this work. ...
doi:10.1145/1168917.1168877
fatcat:lio4fpc6xndzrgmlm2jwz653qm
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
2006
SIGPLAN notices
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As benchmarks exhibit different amounts of task, data, and pipeline parallelism, we exploit all types of parallelism in a unified manner in order to achieve this generality. ...
In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. ...
Acknowledgments We would like thank the members of the StreamIt team, both past and present, and especially Jasper Lin, Rodric Rabbah, and Allyn Dimock for their contributions to this work. ...
doi:10.1145/1168918.1168877
fatcat:k4p3bzg22fbivexpq6s2mkycr4
Automatic generation of hardware/software interfaces
2012
Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '12
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for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application. ...
Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously ...
help with FPGA platforms, and Martin Rinard of CSAIL for his input in the writing process. ...
doi:10.1145/2150976.2151011
dblp:conf/asplos/KingDA12
fatcat:muhuovmeibeixajcvcn5shf2sq
Automatic generation of hardware/software interfaces
2011
Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11
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for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application. ...
Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously ...
help with FPGA platforms, and Martin Rinard of CSAIL for his input in the writing process. ...
doi:10.1145/2038698.2038700
dblp:conf/cases/Arvind11
fatcat:ph5soruycbfezd2xmk2tshyr4y
Automatic generation of hardware/software interfaces
2012
SIGARCH Computer Architecture News
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for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application. ...
Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously ...
help with FPGA platforms, and Martin Rinard of CSAIL for his input in the writing process. ...
doi:10.1145/2189750.2151011
fatcat:lfqc37ya6beftjfax3p4xnzmtu
From software to accelerators with LegUp high-level synthesis
2013
2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)
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This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements ...
The final application then executes on an automatically-generated software/hardware coprocessor system. ...
The financial support of the Natural Sciences and Engineering Research Council of Canada (NSERC) and Altera Corporation is gratefully acknowledged. ...
doi:10.1109/cases.2013.6662524
dblp:conf/cases/CanisCFLHCGQACBA13
fatcat:mkl646vbefa43irr2i725vmh6u
Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces
2013
Journal of Integrated Circuits and Systems
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For a set of 9 ben- chmarks without memory operations, we generated pipelined hardware versions of the loops and esti-mate that the presented loop pipelining technique increases the average speedup of ...
The technique transforms the body of Mega-blocks into an acyclic dataflow graph which can be fully pipe-lined and is based on the atomic execution of loop iterations. ...
An im-portant part of this methodology is the identification and mapping of application hotspots to hardware (referred herein as hardware/software partitioning, or simply partitioning). ...
doi:10.29292/jics.v8i1.373
fatcat:6fvot4onazgjbejixtutauyymq
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