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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
2015
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. ...
Index Terms-Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency. ...
Paper Contribution In this paper, we propose an aging-aware reliable multiplier design with a novel adaptive hold logic (AHL) circuit. ...
doi:10.1109/tvlsi.2014.2311300
fatcat:3ei422f35fcn7folp4fxpfzwpm
Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic
unpublished
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Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. ...
Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency. ...
Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. ...
fatcat:e4pj3322frevbkqzgxxe3grdv4
AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC
2016
International Journal of Recent Trends in VLSI,Embedded Systems and Signal Processing
unpublished
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Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. ...
Keywords Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency. ...
This paper has been organized in the following way, we propose an aging-aware reliable multiplier design with novel adaptive hold logic (AHL) circuit. ...
fatcat:kntthdkytve23je5zebnnhn4bi
Reliable High Performance Multiplier with Adaptive Hold Logic for Aging Awareness
2016
Indian Journal of Science and Technology
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Design of Multiplier circuit using Adaptive Hold Technique is proposed. ...
As the rapid developments in technology required, many researchers are going to design multipliers which offers an efficient design aspect with respect to the speed and power consumption. ...
High Performance Multiplier with Adaptive Hold Logic for Aging Awareness one or two cycle. ...
doi:10.17485/ijst/2016/v9i29/90859
fatcat:vdskuzy2qvghvdmxtpmq25dazq
Razor Based Low-Power Multiplier with Variable Latency Design
2016
International Journal of Science and Research (IJSR)
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In this multiplier the performance degradation due to the aging effect can be minimized using Adaptive Hold Logic. This logic is applied to column and row bypassing multipliers. ...
Hence it is required to design a reliable low power high performance multiplier. In this paper we propose a Razor based low power multiplier with variable latency design. ...
Paper contribution In this paper the Aging aware reliable multipliers has been proposed with adaptive hold logic based on the variable latency design. ...
doi:10.21275/v5i5.nov163600
fatcat:o4l4emd73ndstorii3kq2abvcu
Aging –Aware Multiplier with AHL using FPGA
2017
International Journal of Emerging Engineering Research and Technology
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In this we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit and razor flip flop is used. ...
Therefore it is required to design reliable high performance multipliers. The experimental results show that our proposed architecture with 8x8 and row bypassing and 16x16 column and row bypassing. ...
PROPOSED AGING-AWARE MULTIPLIER The proposed scheme is aging-aware reliable multiplier design as shown in Fig1. ...
doi:10.22259/ijeert.0501003
fatcat:c3xya4fbznh75beq5ptuw6hzq4
A Review on aging aware Reliable Multiplier
2017
IJARCCE
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Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. ...
PROPOSED AGING -AWARE MULTIPLIER This section details the proposed aging-aware reliable multiplier design. ...
RELATED WORK In this paper, we propose an aging-aware reliable multiplier design with a novel adaptive hold logic (AHL) circuit. ...
doi:10.17148/ijarcce.2017.6545
fatcat:ww6mezm2kjhphcjbf2nhqywmaq
Bypassing Multiplier Design Techniques for Detecting Aging Effect
2022
Zenodo
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The various types of bypass multiplier is the latest reliable multiplier layout which decreases switching activities with development in structure. ...
The switching activities must not occur regularly and it can be averted with the aid of the proposed bypassing logic. ...
Adaptive Hold Logic(AHL) The key element of bypassing reliable multiplier is adaptive hold logic system. Fig. 4 indicates the detailed depiction of the AHL circuit. ...
doi:10.5281/zenodo.6787411
fatcat:ioo4ghemgvczhnacfqqvmclmlu
Designing of Multiplier with Improved AHL
2017
International Journal of Computer Applications
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consideration and working to develop delay efficient multiplier with aging aware design using adaptive hold logic which is modified in this work to reduce effective delay to speedup circuit logic. ...
General Terms Multiplier Design on Xilinx IDE 13.1 ...
Fig. 1 1 Fig. 1.4 Adaptive Hold Logic
Figure: 3 3 .1 RTL Schematic of Proposed Architecture
Figure 3 . 3 1 shows the proposed RTL schematic of architecture reliable aging-aware multiplier hold logic ...
doi:10.5120/ijca2017914233
fatcat:trpnxseevzfjdgdklufeu3an2e
A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic
2016
International Journal of Students Research in Technology & Management
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So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. ...
This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit. ...
switching speed.When the An aging-aware multiplier design with novel adaptive hold
biased voltage is removed, the reverse reaction occurs, logic (AHL) circuit [4]. ...
doi:10.18510/ijsrtm.2016.411
fatcat:xjssrmktjvbvff7q7elgqwu6ni
Age-Acknowledging Reliable Multiplier Design with Adaptive Hold Logic
2017
International Journal of Advanced engineering Management and Science
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Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. ...
The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. ...
PAPER CONTRIBUTION In this paper, we propose an aging-aware reliable multiplier design with a novel adaptive hold logic (AHL) circuit. ...
doi:10.24001/ijaems.3.2.2
fatcat:mqavg75zura3jktjcuppvtnga4
Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design using Verilog HDL
2018
International Journal of Computer Applications
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Therefore, it is essential to design dependable high-overall performance multipliers. In this paper, suggest an aging-aware multiplier model with a novel adaptive hold logic (AHL) circuit. ...
Keywords Adaptive hold logic (AHL), Positive bias temperature instability (PBTI), Negative bias temperature instability ...
Paper Contribution In this paper, advise an aging aware reliable multiplier design with novel adaptive hold logic (AHL) circuit. ...
doi:10.5120/ijca2018916547
fatcat:i6kcmk3cyjhvlgnwjmdmp4uwla
Logical Resolving-Based Methodology for Efficient Reliability Analysis
2023
Micromachines
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In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. ...
Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. ...
Furthermore, combining reliability-aware design flow at the circuit level will avoid design costs and complex design convergence. ...
doi:10.3390/mi15010085
pmid:38258204
fatcat:cyhqny7zdfgmhefeuld6hwusca
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
.,
+, TVLSI Oct. 2018 2007-2015
Controlling the Reliability of SRAM PUFs With Directed NBTI Aging
and Recovery. ...
Wu, C., +, TVLSI June 2018 1139-1150 Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
Guest Editorial: Low-Voltage Integrated Circuits and Systems
2017
Circuits, systems, and signal processing
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Interest in developing new design techniques for low-voltage integrated circuits and systems has continued over several decades. ...
Regarding the latter, in some cases even lower V DD can be required, e.g., for circuits supplied with non-conventional energy sources, and devoted to some specific applications, like biomedical implants ...
In the paper "An Aging Aware Reliable FinFET-Based Low-Power 32 Word x 32-bit Register File," a reliable FinFET-based low-power 32 word x 32-bit register file in a 32 nm technology is introduced. ...
doi:10.1007/s00034-017-0666-7
fatcat:433vjlljzbhw7ai46xbht4jv2a
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