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Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference

2016 IEEE Journal of Solid-State Circuits  
INTRODUCTION T HE IEEE International Solid-State Circuits Conference (ISSCC) is the foremost global forum for presenting advances in solid-state circuits and systems-on-a-chip.  ...  A multiple driving and sensing scheme is proposed with a modified Hadamard matrix for position sensing with improving dynamic range and SNR.  ... 
doi:10.1109/jssc.2015.2502519 fatcat:3n3wglza3zgllnjb2bgutznaru

Extending flash lifetime in secondary storage

Chengjun Wang, Sanjeev Baskiyar
2015 Microprocessors and microsystems  
Although some mitigation is achieved by wear leveling, write endurance remains a concern for write intensive applications.  ...  We investigated: (i) a DRAM and a flash disk cache combo within a magnetic disk controller and (ii) a DRAM only cache when flash is a full secondary storage.  ...  ACKNOWLEDGMENTS This work was supported in part by grants DARPA/AFRL FA8750-09-1-0163 and NSF # 0966278  ... 
doi:10.1016/j.micpro.2015.03.002 fatcat:unxxf47dk5abnknnawe5r4zzdu

Robust, Deep, and Reinforcement Learning for Management of Communication and Power Networks [article]

Alireza Sadeghi
2022 arXiv   pre-print
, and decision making schemes that can guarantee robustness, scalability, and situational awareness.  ...  capacitor banks), as well as smart inverters of distributed generation units with cyber-capabilities.  ...  algorithms for managing cyber-physical systems.  ... 
arXiv:2202.05395v1 fatcat:5v3awpoiizaxjjam5deq6yadpa

Survey of Storage Systems for High-Performance Computing

2018 Supercomputing Frontiers and Innovations  
Additional tiers of storage hardware will increase the importance of hierarchical storage management.  ...  Many of these changes will be disruptive and require application developers to rethink their approaches to data management and I/O.  ...  This material reflects only the authors' view and the EU commission is not responsible for any use that may be made of the information it contains.  ... 
doi:10.14529/jsfi180103 fatcat:hi3qctpl7rfvjgl53pxmqwqviy

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM [article]

Ataberk Olgun, Juan Gómez Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oğuz Ergin, Onur Mutlu
2023 arXiv   pre-print
Using PiDRAM, we implement and evaluate two state-of-the-art PuM techniques: in-DRAM (i) copy and initialization, (ii) true random number generation.  ...  Since DRAM is the dominant memory technology as main memory in current computing systems, these PuM techniques represent an opportunity for alleviating the data movement bottleneck at very low cost.  ...  CLFLUSH or other cache management operations with similar semantics are supported in X86 [68] and ARM architectures [10] .  ... 
arXiv:2111.00082v6 fatcat:3isblw52nvhxjcujjkfasqulj4

Optical RAM and integrated optical memories: a survey

Theoni Alexoudi, George Theodore Kanellos, Nikos Pleros
2020 Light: Science & Applications  
of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for  ...  This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics  ...  Acknowledgements This work has received funding from the Hellenic Foundation for Research and Innovation (HFRI) and the General Secretariat for Research and Technology (GSRT) through the ORION project  ... 
doi:10.1038/s41377-020-0325-9 pmid:32509298 pmcid:PMC7248061 fatcat:iok7sgr4nvfvjkjxwxtodo7pl4

Phase-change memory

Omer Zilberberg, Shlomo Weiss, Sivan Toledo
2013 ACM Computing Surveys  
This article surveys the current state of phase-change memory (PCM) as a nonvolatile memory technology set to replace flash and DRAM in modern computerized systems.  ...  The designs surveyed in this article include read before write, wear leveling, write cancellation, write pausing, some encryption schemes, and buffer organizations.  ...  Other-Solid-State Memory Alternatives Besides PCM and NAND flash, there are other alternative memory technologies considered for solid-state memories.  ... 
doi:10.1145/2480741.2480746 fatcat:lvyy3ibbuvaszdk3wazh2tiowy

RapiLog

Gernot Heiser, Etienne Le Sueur, Adrian Danis, Aleksander Budzynowski, Tudor-loan Salomie, Gustavo Alonso
2013 Proceedings of the 8th ACM European Conference on Computer Systems - EuroSys '13  
Database management systems provide updates with guaranteed durability in the presence of OS crashes or power failures.  ...  We would like to thank Leonid Ryzhyk, Adam Walker and John Keys for providing the Termite IDE driver, and Peter Chubb for building the power-out notification device and helping in many places.  ...  We would finally like to thank the anonymous EuroSys reviewers, and especially our shepherd Steven Hand, for insightful comments which helped to improve the paper.  ... 
doi:10.1145/2465351.2465383 dblp:conf/eurosys/HeiserSDBSA13 fatcat:rnnuueocizgdxjysli5v2akqeu

OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface

Yun-Sheng Chang, Ren-Shuo Liu
2019 USENIX Annual Technical Conference  
Consumer-grade solid-state drives (SSDs) guarantee very few things upon a crash.  ...  We also thank the National Center for Highperformance Computing (NCHC) of Taiwan for computer time and facilities.  ...  This research is supported in part by NOVATEK Fellowship and in part by the Ministry of Science and Technology (MOST) of Taiwan under grants 108-2218-E-007-023, 108-2218-E-007-021, and 107-2218-E-007-001  ... 
dblp:conf/usenix/ChangL19 fatcat:w4sfka5hevdt5asald4v5gaycq

nvramdisk: A Transactional Block Device Driver for Non-Volatile RAM

Jaemin Jung, Youjip Won
2016 IEEE transactions on computers  
The overhead of supporting transaction accompanies 6% performance penalty in memcachedb operations.  ...  In this work, we developed nvramdisk, a transactional block device driver for byte-addressable NVRAM. nvramdisk effectively addresses the key technical challenges in using a section of NVRAM as a transactional  ...  The authors would like to give special thanks to Myungsik Kim for his help, support, and expert opinions.  ... 
doi:10.1109/tc.2015.2428708 fatcat:t3rpjdzgqvdlhicaiwmk5np4fm

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Gabriel Molas, Etienne Nowak
2021 Applied Sciences  
The potential of these technologies for storage applications addressing various markets and products is discussed.  ...  Finally, we discuss how the rise of artificial intelligence and bio-inspired circuits offers an opportunity for emerging memory technology and shifts the application from pure data storage to storage and  ...  With the emergence of smartphones, tablets, USB drives, and SSD (solid state drives), a new driving force led to a NAND market increase in the digital era of the 2000s [12] .  ... 
doi:10.3390/app112311254 fatcat:pg4iqzg4yfc2vb2lh2mgkyqafq

Solid State Drives: The Beginning of the End for Current Practice in Digital Forensic Recovery?

Graeme Bell, Richard Boddington
2010 Journal of Digital Forensics, Security and Law  
Most people are aware of the transition from portable magnetic floppy discs to portable USB transistor flash devices, yet the transition from magnetic hard drives to solid-state drives inside modern computers  ...  Our experimental findings demonstrate that solid-state drives (SSDs) have the capacity to destroy evidence catastrophically under their own volition, in the absence of specific instructions to do so from  ...  ACKNOWLEDGEMENTS We thank the School of IT at Murdoch University for experimental apparatus. AUTHOR BIOGRAPHIES Dr. Graeme B.  ... 
doi:10.15394/jdfsl.2010.1078 fatcat:xn4my3d3ajex7lxeqlcr5o7w3u

Intelligent controller for a hybrid energy storage system

Maarten Van Jaarsveld, Rupert Gouws
2019 2019 International Multidisciplinary Information Technology and Engineering Conference (IMITEC)  
The board makes use of a quad-core CPU, a builtin Broadcom GPU, RAM and level 1 and 2 cache. MathWorks ® provides a Simulink ® Support Package for the Raspberry Pi.  ...  - Charge (SOC) Depth-of- Discharge Ageing Mechanisms State-of-Health (SOH) 2.2 Case Studies Active Topologies Passive Topologies 2.8 Drive Cycles ECE 15 Drive Cycles NYCC Drive  ...  Hence UC can be used in as part of a HESS for the following purposes: 1) to improve vehicle acceleration; 2) to improve overall drive efficiency; 3) reduce life cycle costs by extending battery life through  ... 
doi:10.1109/imitec45504.2019.9015892 fatcat:qajq65tfjbetjak7zhtypk2kay

2018 Index IEEE Transactions on Computers Vol. 67

2019 IEEE transactions on computers  
., þ, TC March 2018 305-306 Subpage-Aware Solid State Drive for Improving Lifetime and Performance.  ...  ., þ, TC Feb. 2018 222-236 Buffer storage Subpage-Aware Solid State Drive for Improving Lifetime and Perfor- mance.  ... 
doi:10.1109/tc.2018.2882120 fatcat:j2j7yw42hnghjoik2ghvqab6ti

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems [article]

Saba Ahmadian, Farhad Taheri, Hossein Asadi
2019 arXiv   pre-print
We implement an I/O cache scheme using an open-source I/O cache module in Linux operating system.  ...  cache).  ...  Drives (SSDs) as a cache layer for disk subsystem, which is mainly composed from low-performance HDDs and mid-range flash-based SSDs (as depicted in Fig. 1 ).  ... 
arXiv:1912.01555v1 fatcat:tmixr5bbmjgjfphp43g7zqcqvm
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