A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis
[chapter]
2009
IFIP International Federation for Information Processing
Preserved Fulltext
This paper presents a highly accurate method of estimating performances by constructing models of the circuit matrix instead of the traditionally used performance models. ...
Optimization based sizing methods allow automating the synthesis of analog circuits. Automated analog circuit synthesis techniques depend on fast and reliable estimation of circuit performance. ...
The validated matrix model is used for estimating the performance of the analog circuit. ...
doi:10.1007/978-0-387-89558-1_8
fatcat:tekjl5lrvvfkpefzqngq25hi3a
Fast analog circuit synthesis using sensitivity based near neighbor searches
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits. ...
Results show that with hashing and neighbor lookup, synthesis is 6x-13x faster than with the use of matrix models alone. ...
Circuit performance is calculated from the matrix. The focus of this paper is the efficient employment of circuit matrix models for analog synthesis. ...
doi:10.1145/1403375.1403501
fatcat:7xor62iy3zaabmfalgfe6wgjvm
Rapid yield estimation as a computer aid for analog circuit design
1991
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2006; you can also visit the original URL.
The file type is application/pdf.
A rapid yield estimation methodology that aids the analog circuit designer in making design trade-offs that improve yield is presented. ...
This methodology is based on using hierarchical evaluation of analysis equations, rather than simulation, to predict circuit performance. ...
In OASYS, as in several other recent analog synthesis methodologies (e.g., [7] , [ll] ), synthesis is based on approximate analysis equations that predict the performance of a fixed topology in terms ...
doi:10.1109/4.75008
fatcat:q7mrrwcl6jgybjbk4afequjh3m
A brief review of design and simulation methodology in silicon photonics
2022
Tsinghua Science and Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
In this paper, we review the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic ...
Design tools have also evolved from primary devices to complex photonic circuits. ...
Accurate circuit simulation methods can improve the estimation of system performance and increase circuit complexity. ...
doi:10.26599/tst.2021.9010038
fatcat:mb2cwj2tjbfmjavttsektuokki
Efficient parametric yield extraction for multiple correlated non-normal performance distributions of Analog/RF circuits
2007
Proceedings - Design Automation Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this paper we propose an efficient numerical algorithm to estimate the parametric yield of analog/RF circuits with consideration of large-scale process variations. ...
Starting from a set of quadratic performance models, the proposed parametric yield extraction conceptually maps multiple correlated performance constraints to a single auxiliary constraint using a MAX( ...
Most analog/RF performance variations, however, are strongly nonlinear in the presence of large-scale process variations and cannot be accurately approximated by such linear models. ...
doi:10.1145/1278480.1278709
dblp:conf/dac/LiP07
fatcat:242saz7rrfbo7ptkvpnpjrcb7a
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits
2007
Proceedings - Design Automation Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this paper we propose an efficient numerical algorithm to estimate the parametric yield of analog/RF circuits with consideration of large-scale process variations. ...
Starting from a set of quadratic performance models, the proposed parametric yield extraction conceptually maps multiple correlated performance constraints to a single auxiliary constraint using a MAX( ...
Most analog/RF performance variations, however, are strongly nonlinear in the presence of large-scale process variations and cannot be accurately approximated by such linear models. ...
doi:10.1109/dac.2007.375297
fatcat:rqna3xi2tzhshonwnh25wkcw54
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
2019
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Note that this fulltext copy is not of the "primary" version of this work. The version it corresponds to is:
2019 pre-print arXiv:1912.00402v1 fatcat:jvexolgerbfp5p27tdqvj2xhbe
In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. ...
Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. ...
In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. ...
doi:10.23919/date.2019.8714788
dblp:conf/date/ZhangLYYZ019
fatcat:4233bzv7crhe7kpwsv4sbsjafq
A Multi Output Formulation for Analog Circuits Using MOM-SVM
2017
Indonesian Journal of Electrical Engineering and Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
<span>This paper proposes performance based macro modeling of analog circuit using Multi Output Modeling (MOM) with the help of Support Vector Machine (SVM). ...
After tuning the model properly by k-cross validation method, the accuracy was found to be 96.1% which is good enough to make it use for the circuit synthesis purpose.</span> ...
Conclusion This paper shows a novel modeling technique to develop macro-model for analog circuits using MOM-SVM. ...
doi:10.11591/ijeecs.v7.i1.pp90-96
fatcat:ub2m75n2enf45hnou6d4hxkehq
Addressing Substrate Coupling in MixedMode IC's: Simulation and Power Distribution Synthesis
[chapter]
2009
Computer-Aided Design of Analog Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. ...
Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. ...
The synthesis tool, RAIL, creates analog power distribution while minimizing noise coupling to sensitive analog circuits. ...
doi:10.1109/9780470544310.ch39
fatcat:sm7dia4ouvekxiy2gxgtdild6a
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis
1994
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. ...
Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. ...
The synthesis tool, RAIL, creates analog power distribution while minimizing noise coupling to sensitive analog circuits. ...
doi:10.1109/4.278344
fatcat:qvdcxh5k4faczoor4zbestuc6i
Synthesis of high-performance analog circuits in ASTRX/OBLX
1996
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is application/pdf.
To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTWOBLX has resynthesized circuits in ...
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. ...
In particular, the authors wish to thank S. Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. ...
doi:10.1109/43.489099
fatcat:awvixpettzc5rpw6gssllbktn4
Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX
[chapter]
2009
Computer-Aided Design of Analog Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is application/pdf.
To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTWOBLX has resynthesized circuits in ...
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. ...
In particular, the authors wish to thank S. Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. ...
doi:10.1109/9780470544310.ch14
fatcat:uchovdny5bgbfcmtbnmglshqia
Free Software for Analog and Digital Design
2021
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
PSSOH paper on free software for analog and digital design. The lecture was recorded and the video of presentation held by Assist. Prof. ...
Synthesis in OpenLane flow is performed by Yosys+ABC [4] . ...
Instead of relying on device models to perform numerical integration and fill-in MNA matrix, as is the case in SPICE-based simulators, Xyce uses Differential-Algebraic Equation (DAE) formulation. ...
doi:10.5281/zenodo.6506432
fatcat:yn3fyiaulvcprja5nkchermmae
Fast Macromodel-based Signal Integrity Assessment for RF and Mixed-Signal Modules
2007
2007 IEEE International Symposium on Electromagnetic Compatibility
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
In particular, we introduce a complexity reduction process that enables the Signal Integrity verification via analog circuit simulations, and we apply the methodology to complex radio transceiver chips ...
in order to characterize the influence of parasitic elements on the signal processing performance of the system. ...
Also, the complexity of the overall model (in terms of circuit elements) is comparable to the complexity that would be obtained by using common poles for all scattering responses, since a circuit synthesis ...
doi:10.1109/isemc.2007.146
fatcat:zoqqplkdufhnvaf6ow7yukpbsu
2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28
2009
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
., +, TCAD Nov. 2009 1627-1640 Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. ...
., +, TCAD Oct. 2009 1597-1608
Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects
Using a Matrix Rational Approximation. ...
Formal verification Dependent-Latch Identification in Reachable State Space. ...
doi:10.1109/tcad.2009.2036802
fatcat:hxyu2mmrnzfnbi6qlt6bklkgku
« Previous
Showing results 1 — 15 out of 12,327 results