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A complete real-time 802.11a baseband receiver implemented on an array of programmable processors
2008
2008 42nd Asilomar Conference on Signals, Systems and Computers
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This paper reports the design and software implementation of a real-time digital baseband receiver compliant with the IEEE 802.11a standard on the AsAP2 platform, a DSP chip multiprocessor. ...
The computational platform consists of an array of programmable processors and configurable accelerators interconnected in a 2-D mesh network that are well matched for implementing complex DSP and embedded ...
ACKNOWLEDGMENTS The authors would like to thank members of VCL for discussion and assistance. ...
doi:10.1109/acssc.2008.5074384
fatcat:pgygeligo5fxjo4z2o5q6drtau
Implementation, integration, and verification of MIMAX WLAN modem
2011
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)
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This paper describes the concept, implementation, integration, and verification of an RF-MIMO wireless LAN system called MIMAX. ...
A test setup for trying out the complete MIMAX modem in laptop form factor is presented. ...
ACKNOWLEDGMENT The research leading to these results has received funding from the European Community's Seventh Framework Programme FP7 (2007 -2013) under the grant agreement no. 213952 also referred as ...
doi:10.1109/recosoc.2011.5981523
dblp:conf/recosoc/StamenkovicTWIRD11
fatcat:mkgh5zwmzrfubpiyakm2hvd2oq
Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore
2011
2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
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We present a software-only implementation of an IEEE 802.11a (WiFi) receiver optimized for Intel multicore platforms. ...
Our hand-optimized implementation achieves real-time for all data rates up to the maximum of 54 Mbit/s on a Core i7, clocked at 3.3 GHz, and for up to 12 Mbit/s on an Atom, clocked at 1.6 GHz, using two ...
This could be a field programmable gate array (FPGA), a digital signal processor (DSP), a full-fledged general purpose processor (GPP), or any combination of those. ...
doi:10.1109/icassp.2011.5946826
dblp:conf/icassp/BergerAVFP11
fatcat:h6qzkhyixfb25j4jrmafbbhes4
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
2010
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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For evaluating the efficiency of this platform, a complete 802.11a WLAN baseband receiver was implemented. ...
It has a real-time throughput of 54 Mbps with all processors running at 594 MHz and 0.95 V, and consumes an average of 174.8 mW with 12.2 mW (or 7.0%) dissipated by its interconnect links and switches. ...
Mapping of a complete 802.11a baseband receiver using a reconfigurable network that supports long-distance interconnects. mapped and tested a real 802.11a baseband receiver. ...
doi:10.1109/tcad.2010.2048594
fatcat:g4myzx4fr5bs5g6jdqa4ab2eo4
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
2009
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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A complete 802.11a WLAN baseband receiver was implemented on this platform. ...
It has a real-time throughput of 54 Mbps with all processors running at 594 MHz and 0.95 V, and consumes an average 174.76 mW with 12.18 mW (or 7.0%) dissipated by its interconnection links. ...
Acknowledgments The authors thank Zhiyi Yu who inspired the original idea on source-synchronous clocking technique for many-core design. ...
doi:10.1109/nocs.2009.5071470
dblp:conf/nocs/TranTB09
fatcat:fwalhuitkfhczmvo5gflqv7kgy
On the single-chip implementation of a Hiperlan/2 and IEEE 802.11a capable modem
2001
IEEE personal communications
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The work presented in this article discusses aspects of implementing a complete Hiperlan/2 and IEEE 802.11a compliant modem, including the physical layer as well as the data link control layer, into a ...
Broadband wireless communication is the key technology to a new generation of products in the consumer market. ...
To simplify the debugging of the executable, running on a 32bit ARM7TDMI RISC processor, the real-time operating system pSOS is deployed. ...
doi:10.1109/98.972168
fatcat:l4yy3s7klvanfphfwtix54nq5a
Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor
2003
Japanese Journal of Applied Physics
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In order to verify the real time operation, the IEEE802.11a baseband OFDM test-bed with the newly proposed Radix-N pipeline FFT processor is implemented using field programmable gate array (FPGA) devices ...
In this paper, a new Radix-N pipeline fast Fourier transform (FFT) processor for the implementation of IEEE 802.11a baseband orthogonal frequency division multiplexing (OFDM) modem for wireless local area ...
An Implementation Example The implemented test-bed of IEEE 802.11a baseband OFDM modem block is shown in the Fig. 6 . ...
doi:10.1143/jjap.42.2176
fatcat:wvokoy4bujcrfnngixbjgjwd2m
Atomix: A Framework for Deploying Signal Processing Applications on Wireless Infrastructure
2015
Symposium on Networked Systems Design and Implementation
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We show that applications built in Atomix achieve hardware-like performance by building an 802.11a receiver that operates at high bandwidth and low latency. ...
Multi-processor DSPs have become the platform of choice for wireless infrastructure. ...
Acknowledgments We thank Kyle Jamieson and Jie Xiong for providing us with a reference implementation of SecureArray [29] . ...
dblp:conf/nsdi/BansalSK15
fatcat:zshzl2jezjhurne6ogjzkpiuo4
Software Defined Radio Architecture Survey for Cognitive Testbeds
[article]
2013
arXiv
pre-print
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In this paper we present a survey of existing prototypes dedicated to software defined radio. ...
We propose a classification related to the architectural organization of the pro- totypes and provide some conclusions about the most promising architectures. ...
The ADRES is seen by sandblaster cores are integrated and controlled by an ARM
the processor as a VLIW, while being an array of 16 functional processor. ...
arXiv:1309.6466v1
fatcat:as5hmsdmujdpdnqzbw5mp6oakm
Software defined radio architecture survey for cognitive testbeds
2012
2012 8th International Wireless Communications and Mobile Computing Conference (IWCMC)
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In this paper we present a survey of existing prototypes dedicated to software defined radio. ...
We propose a classification related to the architectural organization of the prototypes and provide some conclusions about the most promising architectures. ...
It is constituted of an ARM processor for control and three ASIPs for coarse time synchronisation on different front ends. ...
doi:10.1109/iwcmc.2012.6314201
dblp:conf/iwcmc/DardaillonMRS12
fatcat:epldbj6kbvh37nkjrc25xxtvwm
From WiFi to WiMAX: Efficient GPU-based Parameterized Transceiver across Different OFDM Protocols
2013
KSII Transactions on Internet and Information Systems
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GPU-based implementations are addressed to explain how to accelerate the baseband processing to archive real-time throughput. ...
In this paper, we describe the implementation of parameterized baseband modules using GPUs for two different OFDM protocols, namely, 802.11a and 802.16. ...
Many SDR platforms are currently based on digital signal processors (DSPs) and field programmable gate arrays (FPGAs). ...
doi:10.3837/tiis.2013.08.010
fatcat:qo4g6hrulze5haccbe44dbvpcq
A 167-Processor Computational Platform in 65 nm CMOS
2009
IEEE Journal of Solid-State Circuits
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A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors ...
Programmable processors occupy 0.17 mm and operate at a maximum clock frequency of 1.2 GHz at 1.3 V. ...
A complete and lightly optimized IEEE 802.11a/11g wireless LAN baseband receiver has been completed using 22 programmable processors plus the Viterbi and FFT dedicated-purpose processors. ...
doi:10.1109/jssc.2009.2013772
fatcat:rskm7pf2fbaxdpj2tko4hvuxti
Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
2006
IEEE Circuits and Systems Magazine
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Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring ...
The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level. I. ...
Measured output power spectra of the transmitter baseband channel for a WLAN 802.11a and an UMTS input signal
Fig. 11 . 11 Fig. 11. ...
doi:10.1109/mcas.2006.1607635
fatcat:j7tkg7pf7bhg7f3mycmp3o55zu
Energy-Efficient Software-Defined Radio Solutions For Mimo-Based Broadband Communication
2007
Zenodo
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Publication in the conference proceedings of EUSIPCO, Poznan, Poland, 2007 ...
Capitalizing on a low complexity functional architecture, a heterogeneous MPSOC platform currently designed in 90nm CMOS and an integrated software development flow, real time operation with an average ...
The radio digital processing is there implemented as software components on a highly programmable platform. ...
doi:10.5281/zenodo.40436
fatcat:gxvopbtfvnd53lvetqt23vr62m
State of the art baseband DSP platforms for Software Defined Radio: A survey
2011
EURASIP Journal on Wireless Communications and Networking
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Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. ...
This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends. ...
The purpose of SDR is to enable a programmable solution based on Digital Signal Processing (DSP) software running on a set of programmable processors and accelerators. ...
doi:10.1186/1687-1499-2011-5
fatcat:apmz6jd4cbdcrpb76qnungmirq
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