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Ranga Vemuri
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Publications
- 2007
- [c151]Huiying Yang, Ranga Vemuri:
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. VLSI Design 2007: 201-206 - [i2]Raoul F. Badaoui, Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. CoRR abs/0710.4717 (2007) - 2006
- [c149]Huiying Yang, Ranga Vemuri:
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. DATE 2006: 283-284 - [c144]Mukesh Ranjan, Ranga Vemuri:
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS 2006 - [c140]Mengmeng Ding, Ranga Vemuri:
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. VLSI Design 2006: 553-556 - [c139]Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri:
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design 2006: 689-694 - 2005
- [c138]Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235 - [c137]Mengmeng Ding, Glenn Wolfe, Ranga Vemuri:
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. ASP-DAC 2005: 477-482 - [c135]Mengmeng Ding, Ranga Vemuri:
A combined feasibility and performance macromodel for analog circuits. DAC 2005: 63-68 - [c134]Raoul F. Badaoui, Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. DATE 2005: 138-143 - [c131]Mengmeng Ding, Ranga Vemuri:
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. DATE 2005: 1088-1089 - [c124]Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri:
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ACM Great Lakes Symposium on VLSI 2005: 482-487 - [c123]Anuradha Agarwal, Ranga Vemuri:
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. ICCAD 2005: 430-436 - [c122]Anuradha Agarwal, Ranga Vemuri:
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ICCD 2005: 444-452 - [c120]Raoul F. Badaoui, Ranga Vemuri:
Analog VLSI circuit-level synthesis using multi-placement structures. ISCAS (6) 2005: 5978-5981 - [c119]Huiying Yang, Anuradha Agarwal, Ranga Vemuri:
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ISVLSI 2005: 71-76 - [c117]Mengmeng Ding, Ranga Vemuri:
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. VLSI Design 2005: 528-534 - 2004
- [c113]Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri:
Fast and accurate parasitic capacitance models for layout-aware. DAC 2004: 145-150 - [c111]Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609 - [c109]Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri:
Accurate Estimation of Parasitic Capacitances in Analog Circuits. DATE 2004: 1364-1365 - [c101]Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri:
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ACM Great Lakes Symposium on VLSI 2004: 271-276 - [c99]Ranga Vemuri, Glenn Wolfe:
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. ICCAD 2004: 931-938 - 2003
- [j18]Glenn Wolfe, Ranga Vemuri:
Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 198-212 (2003) - [c93]Glenn Wolfe, Mengmeng Ding, Ranga Vemuri:
Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. VLSI-SOC 2003: 142- - [c92]Hemanth Sampath, Ranga Vemuri:
MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. VLSI-SOC 2003: 416-421
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