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Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints ...
nonlinear programming; • An accurate model for parasitic resistance and capacitance extraction of parallel structures is applied; • Parasitic matching effects are thoroughly regarded in the parasitic-aware ...
doi:10.1145/1233501.1233570
dblp:conf/iccad/JangkrajarngZBKS06
fatcat:xf5dahmkordxvnhe6rle3twp2i
Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints ...
nonlinear programming; • An accurate model for parasitic resistance and capacitance extraction of parallel structures is applied; • Parasitic matching effects are thoroughly regarded in the parasitic-aware ...
doi:10.1109/iccad.2006.320056
fatcat:zdazrlmjtrgs7e665sqwan2vfy
Fast capacitance extraction in multilayer, conformal and embedded dielectric using hybrid boundary element method
2007
Proceedings - Design Automation Conference
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experience in EDA technologies and methodologies that include VLSI physical layout design and logic synthesis, interconnect optimization, timing analysis, circuit integrated and design for manufacturability ...
An Electronic Design Automation(EDA) Engineer within the IC design industry ♦ 3+ years experience in interconnect parasitic extraction and 1+ years in DFM aware parasitic extraction. ♦ Advanced research ...
Investigated a new accurate and simple closed-form approach to compute the effective capacitance
and model ...
doi:10.1145/1278480.1278687
dblp:conf/dac/ZhouLS07
fatcat:ajwa26ykwza3xkv55r4s6hdnbq
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method
2007
Proceedings - Design Automation Conference
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experience in EDA technologies and methodologies that include VLSI physical layout design and logic synthesis, interconnect optimization, timing analysis, circuit integrated and design for manufacturability ...
An Electronic Design Automation(EDA) Engineer within the IC design industry ♦ 3+ years experience in interconnect parasitic extraction and 1+ years in DFM aware parasitic extraction. ♦ Advanced research ...
Investigated a new accurate and simple closed-form approach to compute the effective capacitance
and model ...
doi:10.1109/dac.2007.375280
fatcat:md6ijpfxa5hxfbuys5da6eovti
Efficient optimization of fully-integrated inductive DC–DC converters comprising tapered inductor layout synthesis and temperature effects
2013
Analog Integrated Circuits and Signal Processing
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The optimization framework is validated by co-optimizing the design parameters and the tapered inductor layout for a fully-integrated DC-DC boost converter in a 0.13µm CMOS technology. ...
This work presents a framework to co-optimize the circuit and the layout parameters of fully integrated inductive DC-DC converters. ...
Acknowledgements Parts of this work have been funded by IWT and the FP7 SMAC project. ...
doi:10.1007/s10470-013-0215-7
fatcat:ognuoz24n5dcnkxsojob65odte
Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric
2010
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10
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The proposed procedure quickly selects the best set of patterns for testing the critical paths under power supply noise and crosstalk effects. ...
Power supply noise and crosstalk are considered as the two major noise sources that negatively impact signal integrity in digital integrated circuits. ...
In the pre-processing step, we extract the physical parasitic effects of the layout using a commercial tool and acquire wire resistances, capacitances to ground, and coupling capacitances. ...
doi:10.1145/1785481.1785512
dblp:conf/glvlsi/MaLTAG10
fatcat:uoewcofz3zbvhj7iv7glc46rwa
Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects
2012
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
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An optimization framework is used to acquire an optimal converter, focusing on the onchip inductor as well as on the accurate layout-based modeling of temperature effects. ...
For the inductor in inductive DC-DC converters, a tapered topology is introduced. A fully-integrated DC-DC boost converter is designed and optimized in a 0.13 µm CMOS technology. ...
NSGA-II [4] , SPEA [5] and ALPS [6] . This combination yields an efficient and robust framework, applicable for layout-aware optimization of a relatively large class of analog building blocks. ...
doi:10.1109/smacd.2012.6339411
fatcat:7ob7ovo37nhtzbychrr6im5loi
Polynomial metamodel based fast optimization of nano-CMOS oscillator circuits
2014
Analog Integrated Circuits and Signal Processing
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Polynomial metamodels are created from post-layout parasitic netlists and provide an accurate representation for each Figure- of-Merit (FoM) over the entire design space of the AMS-SoC component. ...
Thus, the paper demonstrates that the polynomial metamodeling approach to the design problem is an effective and accurate means for fast design space exploration and optimization. ...
This makes the design exploration fast and yet accurate as the polynomial metamodels are ab initio generated accounting for parasitic effects. ...
doi:10.1007/s10470-014-0284-2
fatcat:i4gufaxsozeq5iicxbgr3k6mlu
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling
2011
2011 12th International Symposium on Quality Electronic Design
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A ring oscillator is designed for a 45 nm nano-CMOS technology and the post-layout parasitic netlist is used as a test case for a comparative study. ...
The approach relies on the fact that optimization carried out over a metamodel (which is an abstracted representation of the circuit model) instead of the actual circuit will allow fast design space exploration ...
RF-specific transistor sizing with explicit parasitic estimates is given in [24] . A layout-aware modeling approach for analog synthesis is given in [25] and [26] . ...
doi:10.1109/isqed.2011.5770758
dblp:conf/isqed/GaritselovMK11
fatcat:uniys6zgqnbpndr5xcn6poxw3m
Fast statistical analysis of RC nets subject to manufacturing variabilities
2011
2011 Design, Automation & Test in Europe
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The sensitivity-based layout-to-circuit extraction generates first-order Taylor series approximations of resistances and capacitances with respect to multiple geometric parameter variations. ...
This paper proposes a highly efficient methodology for the statistical analysis of RC nets subject to manufacturing variabilities, based on the combination of parameterized RC extraction and structure-preserving ...
One is parameterized Layout Parasitic Extraction (LPE), which models the effect of physical variations by generating linear or quadratic models of capacitances and resistances as a function of process ...
doi:10.1109/date.2011.5763012
dblp:conf/date/BiKVSM11
fatcat:2jakcun54vaflpz6bcv23hhx6i
PowerSynth progression on layout optimization for reliability and signal integrity
2020
Nonlinear Theory and Its Applications IEICE
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A generic and scalable constraint-aware layout engine is developed to process generic types of devices, traces, and connectors in power modules. ...
Finally, a new post-layout optimization step is included in the flow as an improvement of design for manufacturability and reliability. ...
We further optimized our codebase to convert and compile the model in C programming language, which enables a fast and accurate layout optimization for high-voltage and high-current reliability consideration ...
doi:10.1587/nolta.11.124
fatcat:sqvepm4ghncyzcodfbukoozggy
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
2009
Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09
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To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized for power (including leakage), performance, parasitics and process ...
In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. ...
In [8] , an LC VCO has been subjected to a parasitic-aware synthesis. A parasitic and process aware design flow has been proposed in [10] . ...
doi:10.1145/1531542.1531612
dblp:conf/glvlsi/GhaiMK09
fatcat:sw3u4f562rgwrhbknswmn5qfv4
A Python-based layout-aware analog design methodology for nanometric technologies
2011
2011 IEEE 6th International Design and Test Workshop (IDT)
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This paper presents a methodology for procedural layout-aware design for nanometric technologies. ...
Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. ...
Transistor folding technique is commonly used to reduce parasitic capacitance and gate resistance [1] , [2] allowing more accurate geometries and providing better electrical performance. ...
doi:10.1109/idt.2011.6123103
dblp:conf/idt/YoussefJDIL11
fatcat:mc6afa62s5e7fcpp6s57j7c5oa
Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies
2003
IBM Journal of Research and Development
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Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects. ...
Complex rf-and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design iterations be kept to a minimum. ...
Specifically, we acknowledge the IBM Semiconductor Research and Development Corporation (SRDC) and Communication Research and Development Corporation for support. ...
doi:10.1147/rd.472.0139
fatcat:pejbk72rafbfxkagylkctnet24
A seamless representation for coupling transistor sizing with nanometric CMOS layout generation
2011
2011 20th European Conference on Circuit Theory and Design (ECCTD)
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The layout is generated with the layout dependent parasitics, including stress effects. These parasitics are then taken into account by the sizing operators. ...
In the proposed method, the device sizes and biases are first computed using dedicated sizing operators based on the MOS transistor model and the foundry Design Kit. ...
To our knowledge, very few number of tools provide the designer with a fast and accurate way to realize different layouts for the same analogue atomic function. ...
doi:10.1109/ecctd.2011.6043356
dblp:conf/ecctd/YoussefJDIL11
fatcat:g6wfmgmhcjbbffo3uou7rh3nn4
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