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State-of-the-Art on Analog Layout Automation
[chapter]
2016
Analog Integrated Circuit Design Automation
Preserved Fulltext
layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. ...
This methodology can be found in recent literature with different designations like parasitic-aware, layout-aware and layout-driven synthesis (or sizing). ...
doi:10.1007/978-3-319-34060-9_2
fatcat:7flyp6nwd5aprexg2ccab4abau
State of the Art on Analog Layout Automation
[chapter]
2012
SpringerBriefs in Applied Sciences and Technology
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layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. ...
This methodology can be found in recent literature with different designations like parasitic-aware, layout-aware and layout-driven synthesis (or sizing). ...
doi:10.1007/978-3-642-33146-6_2
fatcat:miizfmqdqbd67azo7hb3j72xna
Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop
2018
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Experiments are conducted over a widely-used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process ...
simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. ...
Proposed two-step RF-specific layout-aware synthesis flow: (a) Integrated inductor design using Gaussian-process surrogate modeling and optimal IDS determination, and, (b) Layout-aware circuit sizing loop ...
doi:10.1109/tcad.2018.2834394
fatcat:lzwwmx7ad5fsnfpnvpt4b7h2xm
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
[article]
2022
arXiv
pre-print
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In this paper, we summarize the state-of-the-art in AL/ML for circuit design/optimization, security and engineering challenges, research in security-aware CAD/EDA, and future research directions and needs ...
for using AI/ML for security-aware circuit design. ...
.,, the design including layout parasitics. ...
arXiv:2204.09579v2
fatcat:tebjzerhfvaepbwmka7ipiccxy
Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX
[chapter]
2009
Computer-Aided Design of Analog Integrated Circuits and Systems
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To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTWOBLX has resynthesized circuits in ...
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. ...
In particular, the authors wish to thank S. Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. ...
doi:10.1109/9780470544310.ch14
fatcat:uchovdny5bgbfcmtbnmglshqia
Synthesis of high-performance analog circuits in ASTRX/OBLX
1996
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTWOBLX has resynthesized circuits in ...
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. ...
In particular, the authors wish to thank S. Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. ...
doi:10.1109/43.489099
fatcat:awvixpettzc5rpw6gssllbktn4
Implementation-Aware System-Level Simulations for IR-UWB Receivers: Approach and Design Methodology
[chapter]
2011
Novel Applications of the UWB Technologies
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a unique simulation tool for both analog and digital circuits disregarding the math they are based on. ...
The methodology is based on the use of the modular formalism of VHDL, working for the design of digital circuits, properly extended for use in analog continuous-time circuits with AMS extensions. ...
Implementation-Aware System-Level Simulations for IR-UWB Receivers: Approach and Design Methodology, Novel Applications of the UWB Technologies, Dr. ...
doi:10.5772/18010
fatcat:xzxxyerotbhj3oczxslsjx2tfu
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs
[article]
2022
arXiv
pre-print
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Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. ...
Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. ...
[67] predict layout parasitics and device parameters of AMS circuits, to render pre-layout simulations more efficient and accurate. ...
arXiv:2211.16495v1
fatcat:unypchxwana5lctbl2pi56773y
Analog Circuit Design in Nanoscale CMOS Technologies
2009
Proceedings of the IEEE
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Classic analog designs are being replaced by digital methods, using nanoscale digital devices, for calibrating circuits, overcoming device mismatches, and reducing bias and temperature dependence. ...
Analog circuit simulation and verification techniques have never been proper substitutes for good analog system, circuit, and physical layout design. ...
Optimizing MOSFETs is challenging due to conflicting device performance requirements for digital and analog circuits. For digital circuits, the I on =I off tradeoff dominates. ...
doi:10.1109/jproc.2009.2024663
fatcat:mzxbcrpd4nht3hwayzlgibal2q
Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models
Proceedings Design, Automation and Test in Europe Conference and Exhibition
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We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. ...
The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. ...
The performance of an analog circuit is sensitive to the parasitic effects introduced during the subsequent layout phase. ...
doi:10.1109/date.2004.1268911
dblp:conf/date/RanjanVASVG04
fatcat:qngnl7nskvewfarjrfsqwy4mu4
Use of symbolic performance models in layout-inclusive RF low noise amplifier synthesis
2004 IEEE International Conference on Cluster Computing (IEEE Cat. No.04EX935)
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The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics symbolically into the SPMs before the start of synthesis. ...
In this paper we present a layout-in-loop synthesis method for radio-frequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and high-frequency extraction techniques ...
A similar approach was proposed by us in [10] but it is limited to linear analog circuit synthesis and the parasitic-inclusion techniques are relevant only to rule-based extractors. ...
doi:10.1109/bmas.2004.1393995
fatcat:vcgv4xtgpbbi7hsbu2ggifznnm
Logic synthesis in a nutshell
[chapter]
2009
Electronic Design Automation
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About This Chapter What is logic synthesis? As the name itself suggests, logic synthesis is the process of automatic production of logic components, in particular digital circuits. ...
It is a subject about how to abstract and represent logic circuits, how to manipulate and transform them, and how to analyze and optimize them. Why does logic synthesis matter? ...
In calculating wire delays, timing data arising from the parasitic capacitances and resistances of wires can be estimated through simulation or can be back-annotated from the final circuit layout. ...
doi:10.1016/b978-0-12-374364-0.50013-8
fatcat:zuz2226qfjcgzlgni2vtqc4fnu
2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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on Mutual Information Optimization; TCSII Dec. 2020 3577-3581 Qian, K., see Zou, W., 1279-1283 Qian, K., see Qian, L., 2943-2947 Qian, L., Li, D., Qian, K., Ye, Y., Xia, Y., and Mak, T., A Fast-Transient ...
3496 Qin, W., see Lu, Q., 2983-2987 Qin, Y., see Xu, Y., TCSII Nov. 2020 2367-2371 Qin, Z., Qiu, Y., Sun, H., Lu, Z., Wang, Z., Shen, Q., and Pan, H., A Novel Approximation Methodology and Its Efficient ...
., +, TCSII Feb. 2020 385-389 Error-Aware Design Procedure to Implement Hardware-Efficient Logarithmic Circuits. ...
doi:10.1109/tcsii.2020.3047305
fatcat:ifjzekeyczfrbp5b7wrzandm7e
Defense Advanced Research Projects Agency (Darpa) Fiscal Year 2016 Budget Estimates
2015
Zenodo
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The Defense Advanced Research Projects Agency (DARPA) FY2016 amounted to $2.868 billion in the President's request to support high-risk, high-reward research. ...
FY 2016 -Design, fabricate and test the second generation optical receiver chip with 8 channels and optimized optical response to minimize the parasitic capacitance of the circuit. ...
FY 2016 Plans: -Investigate analog intellectual property (IP) reuse techniques for efficient, rapid fabrication of high-performance RF/microwave circuits. ...
doi:10.5281/zenodo.1215366
fatcat:cqn5tyfixjanzp5x3tgfkpedri
Field-Programmable Wiring Systems
2015
Proceedings of the IEEE
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Generally, field-programmable wiring systems support the use of multidomain fabrics that can be used to route analog, power, digital signals, optical, microwave signals, etc. ...
The paper also provides different implementation examples and discusses a list of challenges and recommendations for future work in this area. ...
Technically, we need to be concerned about the introduction of undesired parasitics and compromises in performance when comparing circuit traces and transmission line structures formed in custom design ...
doi:10.1109/jproc.2015.2432123
fatcat:3eofp57jkvhqxohggjfig3jaqe
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