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Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. ...
Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. ...
However when the reconfiguration overhead is small, minimizing the number of partitions may not minimize the overall latency for the design. ...
doi:10.1145/307418.307490
fatcat:z5uborw4pvhn7idgnbcy7fbbsa
Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
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We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. ...
Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. ...
However when the reconfiguration overhead is small, minimizing the number of partitions may not minimize the overall latency for the design. ...
doi:10.1109/date.1999.761123
dblp:conf/date/KaulV99
fatcat:3xsf3soswvhk7kc4yu5g3djp2q
An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
2006
Journal of Computer Science
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In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. ...
The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints. ...
Exploring a very large design space can be too computationally expensive. To limit the number of candidate design points in our work we consider tasks with average or high granularity. ...
doi:10.3844/jcssp.2006.422.430
fatcat:acs2dvanxjgiriqk66svqtwcza
Integrated block-processing and design-space exploration in temporal partitioning for RTR architectures
[chapter]
1999
Lecture Notes in Computer Science
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Block-processing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. ...
We present an automated temporal partitioning and design space exploration methodology that temporally partitions behavior speci cations. ...
In Table 2 , we present the result of temporal partitioning and design space exploration of the DCT for with and without block-processing factors. ...
doi:10.1007/bfb0097945
fatcat:dsjcll5jczcmni27xuxycca4nm
Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)
2007
it - Information Technology
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Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes. ...
This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level ...
For this purpose, we propose the integration of temporal partitioning algorithms into the design space exploration. ...
doi:10.1524/itit.2007.49.3.149
fatcat:gaabsiltkzhq3h54wcou2qw6he
CHARSTAR
2017
SIGARCH Computer Architecture News
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The CHARSTAR design is further optimized for balanced spatiotemporal reconfiguration and also enables efficient joint control of resource and frequency scaling. ...
High-performance architectures are over-provisioned with resources to extract the maximum achievable performance out of applications. ...
ACKNOWLEDGEMENTS The authors would like to thank anonymous reviewers for their insights and comments, Essan Swain for relevant CRIB RTL design and Michael Mishkin for CRIB topology generation, all of which ...
doi:10.1145/3140659.3080212
fatcat:wylho4k46ffcxdm65xf4lrjvla
Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study
2008
EURASIP Journal on Embedded Systems
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New reconfigurable technologies and technology-dependent tools have been developed, but a complete overview of the whole design flow for run-time reconfigurable systems is missing. ...
At implementation level, technology-dependent tools are used to realize the run-time reconfiguration. The design case is part of a WCDMA decoder on a commercially available reconfigurable platform. ...
ACKNOWLEDGMENTS This work was previously supported by the European Commission under the Contract IST-2000-30049 ADRIATIC, and later by Tekes (National Technology Agency of Finland) and VTT under EUREKA ...
doi:10.1155/2008/856756
fatcat:cwmqznktrbgfncsxlo5b2hlc6q
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration
2006
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06
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A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. ...
In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the ...
An efficient algorithm for design space exploration of task implementations inside temporal partitioning is presented and experiments have been shown. ...
doi:10.1145/1150343.1150361
dblp:conf/sbcci/NascimentoLSS06
fatcat:5cqburfnozbkdfai42sphpp3vm
Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration
2007
Journal of Integrated Circuits and Systems
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A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. ...
In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the ...
An efficient algorithm for design space exploration of task implementations inside temporal partitioning is presented and experiments have been shown. ...
doi:10.29292/jics.v2i1.235
fatcat:2tbyedo3jvdn5ptgmasdqn3hxe
Power-performance trade-offs for reconfigurable computing
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
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However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. This work presents a configurationaware data size partitioning approach. ...
In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. ...
The partitioning process must take into account the reconfiguration overhead, and also the configuration pre-fetching technique for reconfiguration latency minimization. ...
doi:10.1145/1016720.1016751
dblp:conf/codes/NogueraB04
fatcat:kmujsufot5gzxnejo72so72t4y
Ecoscale: Reconfigurable Computing And Runtime System For Future Exascale Systems
2016
Zenodo
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Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of partitions in a Partitioned Global Address Space (PGAS), or as a set ...
The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming ...
Such systems combine the flexibility of the reconfigurable fabric with the general-purpose characteristic of CPUs. ...
doi:10.5281/zenodo.34893
fatcat:ocwfndo4vjei3hqucmndj22xu4
COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems
2007
2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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Dynamically reconfigurable systems demand complicated run-time management. ...
We illustrate how COSMOS may be used to capture the dynamic behavior of such systems and emphasize the need for capturing the system aspects of such systems in order to deal with future design challenges ...
Our future work will focus on the run-time management system development and the design space/platform space exploration of the reconfigurable systems with our framework. ...
doi:10.1109/icsamos.2007.4285743
dblp:conf/samos/WuM07
fatcat:5yvw6b6uwvathoyc6a5mo37sp4
Runtime Adaptive Extensible Embedded Processors — A Survey
[chapter]
2009
Lecture Notes in Computer Science
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However, due to the limited area available for implementation of custom instructions in the datapath of the processor core, we may not be able to exploit all custom instruction enhancements of an application ...
Customizable and extensible embedded processors, where the processor core can be enhanced with application-specific instructions, provide a potential solution to this conflicting requirements of performance ...
RISPP requires fast design space exploration technique at runtime to combine appropriate elementary data paths and evaluate tradeoffs between performance and hardware area of the custom instructions [ ...
doi:10.1007/978-3-642-03138-0_23
fatcat:dmhl3mmoxrhfhhcanrryjt5tum
Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip
2007
2007 Design, Automation & Test in Europe Conference & Exhibition
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The performance of the methodology is verified by comparison with existing solutions for several SoC designs. ...
Due to convergence, a growing number of applications are integrated on the same chip. When combined, these applications result in use-cases with different communication requirements. ...
Note that once a solution is found the design space can be explored further by swapping vertices [14] . ...
doi:10.1109/date.2007.364416
dblp:conf/date/HanssonCG07
fatcat:mwrfjbe2pjardfnaiqbl6tffda
A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs
2008
EURASIP Journal on Embedded Systems
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Higher level of abstraction, design space exploration, hardware/software partitioning, codesign, rapid prototyping, virtual component design and integration for heterogeneous architectures; all these topics ...
After a translation to the RTL level a space-time scheduling and hardware partitioning is performed allowing the generation of a run-time reconfiguration controller. ...
doi:10.1155/2008/793919
fatcat:con7yeic5jftrhyp54vdvneoyi
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