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Parallel high-radix Montgomery multipliers
2008
2008 42nd Asilomar Conference on Signals, Systems and Computers
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This paper describes the algorithm and design tradeoffs for multiple hardware implementations of parallel high-radix scalable Montgomery multipliers. ...
Hardware implementations of Montgomery multipliers require choosing a radix, shift direction, and whether to use Booth encoding. ...
In developing a parallel high radix Montgomery multiplier, a designer has three primary design choices: radix, left or right shifting, and use of pre-computed multiples or Booth encoding. ...
doi:10.1109/acssc.2008.5074513
fatcat:r7uxkxvz3vhthpzhoppfi6aeu4
Parallelized Very High Radix Scalable Montgomery Multipliers
Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.
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This paper describes a parallelized very high radix scalable Montgomery multiplier designed for non-redundant FPGA implementations. ...
It improves on the very high radix scalable architecture by using techniques to parallelize the two multiplications within each processing element. ...
The following notation is used to describe this parallelized very high radix Montgomery multiplication. ...
doi:10.1109/acssc.2005.1599950
fatcat:lbm3zz5refax5d5evl2t5z3hwq
Parallelized radix-4 scalable montgomery multipliers
2007
Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07
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This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. ...
This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones. ...
Previous scalable Montgomery multiplier designs include radix-2 [3, 2] , radix-4 [4] , radix-8 [5] , radix-16 [6] , and very high radix [7, 8] . ...
doi:10.1145/1284480.1284562
dblp:conf/sbcci/PinckneyH07
fatcat:wbjirxbcfjazjbxjl6ve66t3xq
Parallelized radix-2 scalable Montgomery multiplier
2007
2007 IFIP International Conference on Very Large Scale Integration
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This paper describes the FPGA implementation of a parallelized scalable radix-2 Montgomery multiplier. ...
On a Virtex-II FPGA, this design can perform 1024-bit modular exponentiation in 6.3 ms using 6006 lookup tables, a 17% speed improvement over the previously fastest scalable radix-2 Montgomery multiplier ...
We have successfully applied the technique to very high radix Montgomery multipliers [4, 5, 6] to shorten the critical path. ...
doi:10.1109/vlsisoc.2007.4402488
dblp:conf/vlsi/JiangH07
fatcat:g3vhf3rnarb5lg6esfrahn6k7q
A Low Latency Montgomery Modular Exponentiation
2020
Procedia Computer Science
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high-radix Montgomery Modular Multiplier. ...
high-radix Montgomery Modular Multiplier. ...
In [8, 9, 10, 11] , the authors implemented high-radix Montgomery Multiplier by using Booth's encoding/recoding schemes. ...
doi:10.1016/j.procs.2020.04.087
fatcat:c2oee4idejgkrlny74zd25riyy
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n)
2008
2008 Asia and South Pacific Design Automation Conference
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The proposed architecture unifies 4 parallel radix-2 16 multipliers in GF (P ) and a radix-2 64 multiplier in GF (2 n ) into a single unit. ...
Moreover, parallel architecture in GF (P ) reduces the clock cycles increased by dual-radix approach. ...
Dual-Radix Unified Multiplier In this section, we propose a Montgomery multiplier architecture which unifies 4 parallel radix-2 16 multipliers in GF (P ) and a radix-2 64 multiplier in GF (2 n ) into a ...
doi:10.1109/aspdac.2008.4484041
dblp:conf/aspdac/TanimuraNKSSTYO08
fatcat:slou4tbb2jbvlhiaofmclux5cm
Quotient Pipelined Very High Radix Scalable Montgomery Multipliers
2006
2006 Fortieth Asilomar Conference on Signals, Systems and Computers
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This paper describes the FPGA implementation of a scalable very high radix Montgomery multiplier using quotient pipelining. ...
This design can perform 1024-bit modular exponentiation in 5.1 ms using 3825 4-input lookup tables and 32 18×18 multipliers, a 20% speed increase over a comparable design without quotient pipelining. ...
Parallelized very high radix design In [1] , an alternative implementation of the Montgomery algorithm based on [5] is discussed. ...
doi:10.1109/acssc.2006.355045
fatcat:xcf3c2g5ijf3jbz44ivbsx6ism
Bipartite Modular Multiplication Method
2008
IEEE transactions on computers
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A radix-4 version of a multiplier based on a radix-4 classical modular multiplier and a radix-4 Montgomery multiplier has been designed and simulated. ...
This paper proposes a new modular multiplication method that uses Montgomery residues defined by a modulus M and a Montgomery radix R whose value is less than the modulus M. ...
The space and time trade-offs for high-radix classical modular multiplication and high-radix Montgomery multiplication, both based on repetitive additions, are detailed in [17] . ...
doi:10.1109/tc.2007.70793
fatcat:a4zvozdu2rdctkecfsrjat3aa4
Quad-Core RSA Processor with Countermeasure Against Power Analysis Attacks
[article]
2020
arXiv
pre-print
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This paper proposes a new parallel, high-radix Montgomery multiplier for 1024 bits multi-core RSA processor. Each computation step operates in radix 4. ...
In this paper, we intend to implement and analyze a power attack resilient quad-core ASIC RSA processor with parallel high-radix Montgomery multiplication in hardware. ...
The parallel core and high radix Montgomery multiplication reduces the total number of clock cycles required, thereby reducing the RSA computational time to 1.2 ms. ...
arXiv:2009.03468v1
fatcat:qgxx5zd7anb6vpzx5wogzhffyu
Bipartite Modular Multiplication
[chapter]
2005
Lecture Notes in Computer Science
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The upper part and the lower part of the multiplier are processed using the interleaved modular multiplication algorithm and the Montgomery algorithm respectively. ...
These two parts are then processed separately, in parallel, potentially doubling the calculation speed. ...
The space and time trade-offs for high radix modular multiplications based on the classical interleaved algorithm and the Montgomery algorithm are detailed in [14] . ...
doi:10.1007/11545262_15
fatcat:lt5u2kh225gwvmvtyy7pjyv5ui
Systematic design of high-radix Montgomery multipliers for RSA processors
2008
2008 IEEE International Conference on Computer Design
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The present paper proposes a systematic design approach to provide the optimal high-radix Montgomery multipliers for an RSA processor satisfying user requirements. ...
A total of 202 designs for 1,024bit RSA processors were obtained for each radix, and were synthesized using a 90-nm CMOS standard cell library. ...
HIGH-RADIX MONTGOMERY MULTIPLIER
A. ...
doi:10.1109/iccd.2008.4751894
dblp:conf/iccd/MiyamotoHAS08
fatcat:rs2mpx6w6rb5fblhjvbvsmi4ga
A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$
[chapter]
2014
Lecture Notes in Computer Science
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The existing high-radix Montgomery multipliers performed a single Montgomery multiplication either in approximately 2n clock cycles, or approximately n cycles but with a very low frequency, where n is ...
In this paper, we first design a novel Montgomery multiplier by combining a quotient pipelining Montgomery multiplication algorithm with a parallel array design. ...
DSP Blocks in FPGAs Dedicated multiplier units in older FPGAs have been adopted in the high-radix Montgomery multiplication implementations for years. ...
doi:10.1007/978-3-662-43414-7_21
fatcat:ybgywvegy5dthddrc4mfnve4im
Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation
2011
International Journal of Reconfigurable Computing
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The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. ...
The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. ...
Forcing a pipelined operation mode and using a high-radix architecture (16 or 32 bits), the multiplexed multipliers ensure the high speed performance provided by systolic architectures, with reduced arithmetic ...
doi:10.1155/2011/127147
fatcat:notenc6k3febnbzwjczrnidcdu
Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture
2016
International Journal of Security and Its Applications
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In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. ...
So, using compact SD representation for the multiplier, the calculation high radix partial multiplication of the P=S(i)+ Y is simplified to binary partition multiplication. ...
The proposed modular multiplication algorithm and architecture has the following distinctive characteristics: a) It utilizes parallel computation to reduce the total computation time. b) It utilizes high-radix ...
doi:10.14257/ijsia.2016.10.10.24
fatcat:a5nxnra7p5h3zfg7sxt6r5gt5u
Page 443 of IEEE Transactions on Computers Vol. 52, Issue 4
[page]
2003
IEEE Transactions on Computers
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Montgomery Multiplier Core
\ slightly modified version of the high-radix Montgomery Multiplier Core in [8] is shown in Fig. 1. ...
We start to build a new unified core by extending a high-radix word-level Montgomery Multiplier core, which implements Algorithm 3.2, to support NTRL with minimal change to the hardware. ...
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