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Authenticated encryption on FPGAs from the static part to the reconfigurable part
2014
Microprocessors and microsystems
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Second, high-throughput GCM architectures are implemented in the reconfigurable part of the FPGA by taking the advantage of slow changing key environments like VPNs and embedded memory protection. ...
First, we present efficient ASIC implementations of AE algorithms, Counter with Cipher Block Chaining Mode (CCM) and Galois Counter Mode (GCM), which are used in the static part of the FPGA in order to ...
Section 4 proposes efficient compact architectures to be used for FPGA bitstream security. Section 5 introduces efficient high speed architectures of AES-GCM using FPGAs. ...
doi:10.1016/j.micpro.2014.03.006
fatcat:bnwwochauzb33ieopovzhighnq
Improved method for parallel AES-GCM cores using FPGAs
2013
2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)
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This paper proposes an efficient method for implementing parallel AES-GCM cores using FPGAs. The proposed method improves the performance of the parallel architecture (Throughput/Slice). ...
Our architectures were evaluated using Virtex5 FPGAs. It is shown that the performance of the presented parallel AES-GCM architecture outperforms the previously reported ones. ...
efficiently (smaller area) on FPGAs as the circuit is specialized for H and a new reconfiguration is uploaded into the FPGA with the new specialization in case of changing the key. ...
doi:10.1109/reconfig.2013.6732299
dblp:conf/reconfig/AbdellatifCM13a
fatcat:f3euscm4xfc5xo3asqbv52apxa
High speed authenticated encryption for slow changing key applications using reconfigurable devices
2013
2013 IFIP Wireless Days (WD)
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This paper describes the benefits of adding key-synthesized property to AES-GCM using FPGAs. ...
It is shown that the performance of the presented AES-GCM architectures outperforms the previously reported ones. ...
On Virtex5, the most efficient implementation reaches the throughput 30.9 Gbps with 2478 slices and 40 BRAMs. ...
doi:10.1109/wd.2013.6686460
dblp:conf/wd/AbdellatifCM13
fatcat:ndvectq23ff4fe6fxmcjnxzzqq
High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier
2018
IEICE Electronics Express
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FPGA implementation on Xilinx FPGA, Virtex5 xc5vlx85 yielded a throughput value of 48.8 Gbps covering area of 6482 slices. ...
The proposed FR-KOA FFM can match the high-efficiency AES we designed to achieve the highly efficient AES-GCM. ...
In this regard, our study is mainly focused on the efficient implementation of AES-GCM with low area and high throughput to make it applicable to highspeed and resource-constrained occasions. ...
doi:10.1587/elex.15.20180559
fatcat:pqnlczpfejc3vgoxfg5bzhkn7u
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
2008
2008 International Conference on Field Programmable Logic and Applications
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A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. ...
For comparison, we also implemented AES-CBC and SHA-256 modules on the same device. ...
The results shows that high-speed and area-efficient implementation is achieved by PR-AES-GCM. ...
doi:10.1109/fpl.2008.4629902
dblp:conf/fpl/HoriSST08
fatcat:nbsr6vm4xjdy7mi2ngzlywplei
Low cost solutions for secure remote reconfiguration of FPGAs
2014
International Journal of Embedded Systems
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This paper presents efficient ASIC implementations of Authenticated Encryption (AE) algorithms, AES-CCM and AES-GCM, which are used in the static part of the FPGA in order to secure the reconfiguration ...
Our focus on state of the art algorithms for efficient implementations leads to propose compact architectures to be used efficiently for FPGA bitstream security. ...
Presented architectures include AES-CCM and AES-GCM which can be used efficiently for secure reconfiguration of FPGAs. ...
doi:10.1504/ijes.2014.063824
fatcat:vly5yref2rdnhpgmpvrfzkzak4
Efficient and high speed key-independent AES-based authenticated encryption architecture using FPGAs
2017
International Journal of Engineering & Technology
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For efficient architectures, FPGA-based systems like AES-GCM and AEGIS-128 plays in the best part of the re-configurability, which supports the security services of such communication and networking systems ...
We possibly focus on the performance of the systems with the high security of the FPGA bit streams. GF (2128) multiplier is implemented for authentication tasks for high-speed targets. ...
The maximum throughput from implementing a single AES-GCM core on Vertex-5 reads as 17.9 Gbps [5] . ...
doi:10.14419/ijet.v7i1.5.9152
fatcat:v37sn7wuznhzxclxkagxl5fmmy
Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array
2018
Journal of Physics, Conference Series
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This paper presents the implementation of AES-GCM by using Field Programmable Gate Array (FPGA) and AES-GCM designs in parallel-pipelined to achieve high performance in term of throughput and latency. ...
The implementation of AES-GCM in FPGA by using 128-bit of input data block, Initialization vector (IV) and Additional Authenticated Data (AAD) to provide a high speed of authenticated encryption/ decryption ...
FPGA Implementation of AES-GCM Architecture The AES-GCM design is programmed in Cyclone V 5CSEMAS5 FPGA on DE1-SoC board. Pins are selected in the pin plan. ...
doi:10.1088/1742-6596/1019/1/012008
fatcat:xuk27k5fyfckzdgvvux53tt5ky
Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application
2020
IEEE Access
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The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it's compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms ...
Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. ...
[52] have presented the high throughput implementation of the AES-GCM algorithm using pipeline architecture on Xilinx Virtex-5 FPGA. Koteshwara et al. ...
doi:10.1109/access.2020.2978665
fatcat:brtrg4e6wzghpcm7z3v73kysj4
High-speed Side-channel-protected Encryption and Authentication in Hardware
[article]
2018
IACR Cryptology ePrint Archive
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This paper describes two FPGA implementations for the encryption and authentication of data, based on the AES algorithm running in Galois/Counter mode (AES-GCM). ...
To the best of our knowledge, our work is (1) the first to describe a throughput-optimized FPGA architecture of AES-GCM, protected against first-order side-channel information leakage, and (2) the first ...
In summary, related work covers high-throughput AES and AES-GCM implementations on the one hand as well as threshold-protected AES implementations on FPGAs and ASICs on the other hand. ...
dblp:journals/iacr/MentensMNV18
fatcat:crpli7vu3bdmzhszj654gfkfbe
Implementation of AES-GCM encryption algorithm for high performance and low power architecture Using FPGA
English
2014
International Journal of Research and Applications
English
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Many of the AES-GCM applications are power and resource constrained and requires efficient hardware implementations. ...
Finally, by implementation of AES-GCM the high-performance GF (2 128 ) multiplier architectures, gives the detailed information of its performance. ...
The aim of such an implementation is to benchmark GCM-AES on FPGA in terms of area, power and speed. ...
doi:10.17812/ijra.1.3(26)2014
fatcat:i7byhqbchbdfdabncy3dje4d54
Unified Hardware for High-Throughput AES-Based Authenticated Encryptions
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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In addition, we confirmed that the proposed hardware is superior to software implementation on general-purpose processor in terms of both throughput and power consumption. ...
., advanced encryption standard (AES), block chaining, and XOR-Encryption-XOR (XEX) scheme), each AEAD is equipped with a unique mode of operation and/or subfunctions, which makes it difficult to integrate ...
One major feature of AES-GCM is that it can be implemented with a high throughput and efficiency, especially when provided with effective hardware support. ...
doi:10.1109/tcsii.2020.3013415
fatcat:2l2cudtkajfyvbh34l7bydmjve
A High-Throughput Hardware Implementation of NAT Traversal For IPSEC VPN
2022
International Journal of Communication Networks and Information Security
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In this paper, we present a high-throughput FPGA implementation of IPSec core. The core supports both NAT and non-NAT mode and can be used in high speed security gateway devices. ...
Results show that the design can gives a peak throughput of 5.721 Gbps for the IPSec ESP tunnel mode in NAT mode and 7.753 Gbps in non-NAT mode using one single AES encrypt core. ...
In order to implement efficiently in hardware, we choose GCM and CTR as modes of operation for AES-256 block cipher. ...
doi:10.17762/ijcnis.v14i1.5260
fatcat:iv5wk77menbu7i3mkzazk7vssu
Efficient key-dependent message authentication in reconfigurable hardware
2011
2011 International Conference on Field-Programmable Technology
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The pipelined GHASH version achieves an authentication throughput of more than 14 Gbit/s on a Spartan-3 FPGA and 292 Gbit/s on a Virtex-6 device. ...
In this paper a customized FPGA implementation of a GHASH function that is used in AES-GCM, a widelyused message authentication protocol, is described. ...
Background on AES-GCM and GHASH functions is provided in Section II. Implementation details of our approach are provided in Section III and experimental results are discussed in Section IV. ...
doi:10.1109/fpt.2011.6132722
dblp:conf/fpt/CrenneCGTD11
fatcat:nttxw3nmdfec3epbzmhsholcea
Ultra-High-Throughput Multi-Core AES Encryption Hardware Architecture
2021
VNU Journal of Science Computer Science and Communication Engineering
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In addition, our design also achieves a high power-efficiency of 2377 Gbps/W and area-efficiency of 833 Gbps/mm2, that is 2.6x and 4.5x higher than those of the other highest throughput of single-core ...
So, security encryptions need high throughput to meet data transfer rates and low latency to ensure the quality of services. ...
Acknowledgment This research is funded by the Ministry of Science and Technology of Vietnam under grant number KC.01.21/16-20 (ADEN4IOT). ...
doi:10.25073/2588-1086/vnucsce.290
fatcat:cgqeopvg4rfghkw3elba3uzqee
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