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2020 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 28
2020
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., Conflux-An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout; TVLSI Feb. 2020 503-515 Holcomb, D., see 2685-2698 Holcomb, D.E., see 1807-1820 Homayoun ...
., +,
TVLSI May 2020 1326-1330
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for
an LSTM Network. ...
., +, TVLSI May 2020 1221-
1229
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for
an LSTM Network. ...
doi:10.1109/tvlsi.2020.3041879
fatcat:33vb2eia2jfjpog4wei4peq5ge
An Overview of Machine Learning within Embedded and Mobile Devices–Optimizations and Applications
2021
Sensors
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Additionally, we discuss the implementation of these algorithms in microcontroller units, mobile devices, and hardware accelerators. ...
(GMMs), and deep neural networks (DNNs). ...
Hardware architecture for the efficient execution of recurrent neural networks (RNN) FPGA based 2016 [23] Hardware Acceleration
Table 23 . 23 Energy-efficient hardware design and architectures. ...
doi:10.3390/s21134412
pmid:34203119
fatcat:dxmshp4frnf4pcookdy3wjl4fi
Schedule
2021
2021 6th International Conference for Convergence in Technology (I2CT)
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5
744
Tavish Jain
Handwriting Recognition for Medical
Prescriptions using a CNN-Bi-LSTM Model
12.45
PM
1.00
PM
6
422
Kundan Kumar
A Novel PID-FOPD Controller for LFC
Including IPFC and ...
5.00
PM
5
81
Madhu M Babu
Reliable Utilization of Hardware for the Real Valued FFT
Architectures
5.00
PM
5.15
PM
6
101
Ambrish Devanshu
Performance Analysis of IM Drive with New Flux ...
doi:10.1109/i2ct51068.2021.9417932
fatcat:werfkg6g65dfzesamouckqcxhy
Programmable processing for the autonomous / connected vehicle : From classical FPGA to adaptable computing Algorithms. Architecture. Realization.Test
2022
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, ADAS/AD system architectures, AI-core, AI-Engine Architecture, design flow, neural networks for gesture recognition, HW-aware perception of neural networks and automotive security and the corresponding ...
The proceedings on "Programmable Processing for the Autonomous / Connected Vehicle" contains the contributions of the 4th workshop on this topic. ...
Additionally, as entire filters are removed, various parallel algorithms and hardware accelerators can be used in a subsequent deployment.
B. ...
doi:10.18725/oparu-42776
fatcat:jdbn7eltoveqxcpbilurdqdmu4
Co-Designing Model Compression Algorithms and Hardware Accelerators for Efficient Deep Learning
2020
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First, we propose specialized architectures for accelerating binarized neural networks on FPGA. ...
In his third year, his focus switched to hardware specialization for deep neural networks and redesigning DNN algorithms to better suit emerging hardware architectures. ...
hardware DNNs acceleration -In response to the previous two trends, computer architecture has moved towards specialized hardware for deep neural networks. ...
doi:10.7298/8fca-8w89
fatcat:b2yepjxhv5ggthqf2pcdnn47eq
Improving low latency applications for reconfigurable devices
2023
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Our second contribution is a new ring-based architecture for low latency, parallel access to FPGA memory. ...
Traditional FPGA memory is formed by grouping block memories (BRAMs) together and accessing them as a single device. Our architecture accesses these BRAMs independently and in parallel. ...
Our second contribution is a new ring-based architecture for low latency, parallel access to FPGA memory. ...
doi:10.25560/101686
fatcat:4kt36y2w4jh6jc42j6tfzkhf3m