A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Filters
A 65 Nm Cryptographic Processor For High Speed Pairing Computation Using Vedic Multiplier
2015
unpublished
Preserved Fulltext
This paper presents a flexible and high-performance processor for cryptographic pair-ings over pairing-friendly curves at high security levels. ...
Infact, when high security is desired, challenges grow even moreenormously for high computational complexity. ...
This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. ...
fatcat:x3i2gtwfbresdi2iq5m7t755gm
Secure LSI Design: Solutions to Hardware Security and Hardware Vulnerability
2018
IEICE ESS FUNDAMENTALS REVIEW
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Yu, et al., A 65 nm cryptographic processor for high speed pairing computation, IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 23, no. 4, pp. 692-701, April 2015. H. Awano, T. ...
Note Comput. sci., vol. 5747, pp. 254-271, 2009. Y. Li, J. Han, S. Wang, et al., An 800 MHz cryptographic pairing processor in 65 nm CMOS, IEEE Asian Solid-State Circuits Conference, 2012. J. Han, Y. ...
doi:10.1587/essfr.12.2_126
fatcat:jpfynaqfi5cx5oxtcwxeer5lxu
New Software Speed Records for Cryptographic Pairings
[chapter]
2010
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is application/pdf.
This paper presents new software speed records for the computation of cryptographic pairings. ...
More specifically, we present a software which computes the optimal ate pairing on a 257-bit Barreto-Naehrig curve in only 4,470,408 cycles on one core of an Intel Core 2 Quad Q6600 processor. ...
We don't know of any other software implementation of a cryptographic pairing on the 128-bit security level that achieves speeds of 7,850,000 cycles or faster on any amd64 processor. ...
doi:10.1007/978-3-642-14712-8_7
fatcat:xrpryttnkzdadloquc7oottogi
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things
2019
Sensors
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
A solution based on Cryptographical Digital Signal Processor (CDSP), a Digital Signal Processor (DSP) based platform combined with dedicated instruction extension, has been proposed, to provide both programming ...
We have also taped out the platform designed for privacy and security concerns of multimedia transferring system based on CDSP. Using TSMC 55 nm technology, it could reach the speed of 360 MHz. ...
Cryptographic Algorithms on a DSP T. Wollinger et al. [8] research how well-suited high-end DSPs are for the AES algorithms. ...
doi:10.3390/s19030556
fatcat:ta7rwefqgrcihgbtybwihl2v2y
Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core
2017
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm 2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW). ...
Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. ...
Acknowledgments: We did not receive funds for covering the costs to publish in open access. ...
doi:10.3390/electronics6020046
fatcat:6xav2duuwffmnhhhjqkjdumch4
A Lightweight AES Coprocessor Based on RISC-V Custom Instructions
2021
Security and Communication Networks
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). ...
To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird ...
Table 4 : 4 Comparison of AES circuits with different implementation routes. [27] [32] [23] AES core Proposed Coprocessor Technology 28 nm 65 nm 65 nm 65 nm Voltage (V) 0.5 1.1 0.8 1.2 Frequency (MHz) ...
doi:10.1155/2021/9355123
fatcat:bgarjbvo25gevh5khd2jt65tjq
Cryptoraptor: High throughput reconfigurable cryptographic processor
2014
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, which is designed to support both today's and tomorrow's symmetric-key cryptography algorithms ...
To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor ...
We have also developed a highly reconfigurable cryptographic processor that can support a wide range of cryptographic algorithms efficiently and has high potential for supporting future algorithms. ...
doi:10.1109/iccad.2014.7001346
dblp:conf/iccad/SayilarC14
fatcat:x3lpnqhitbhxlibxat3sv3bgyu
28nm asynchronous area-saving AES processor with high Common and Machine Learning Side-Channel Attack resistance
2021
IEICE Electronics Express
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. ...
Our proposed asynchronous AES occupies an area of 0.016 𝑚𝑚 2 in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V. ...
Fig. 7 7 Fig. 7 (a) Input and output ports of the AES cryptographic processor. (b) Layout view of the asynchronous AES cryptographic processor. ...
doi:10.1587/elex.18.20210309
fatcat:rl5zo67wi5fghlzpjkk7njidem
2020 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 28
2020
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
., Conflux-An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout; TVLSI Feb. 2020 503-515 Holcomb, D., see 2685-2698 Holcomb, D.E., see 1807-1820 Homayoun ...
Pomeranz, I., TVLSI Jan. 2020 156-162
E
Edge computing
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing
Approximate Computing. ...
., +, TVLSI Aug. 2020 1920-1924 A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process. ...
doi:10.1109/tvlsi.2020.3041879
fatcat:33vb2eia2jfjpog4wei4peq5ge
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
2019
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Other Versions
The cryptographic accelerators are coupled with an on-chip low-power RISC-V processor to benchmark applications beyond DTLS with up to two orders of magnitude energy savings. ...
The test chip, fabricated in 65 nm CMOS, demonstrates hardware-accelerated DTLS sessions while consuming 44.08 uJ per handshake, and 0.89 nJ per byte of encrypted data at 16 MHz and 0.8 V. ...
, Cadence and Mentor Graphics for providing CAD tools. ...
doi:10.1109/jssc.2019.2915203
fatcat:z6b3q6rui5bjlfdlppkdegsbqa
Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves
2012
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper describes a new method to speed up Fp-arithmetic in hardware for pairing-friendly curves, such as the well known Barreto-Naehrig (BN) curves. ...
As an application we show that the performance of pairings on BN curves in hardware can be significantly improved, resulting in a factor 2.5 speed-up compared with state-of-the-art hardware implementations ...
The Montgomery multiplier used in [24] requires 68 cycles for one multiplication. On the other hand, the speed-up for pairing computations is less than the speed-up of the multiplier. ...
doi:10.1109/tc.2011.78
fatcat:zeafwfk2mvf2xf7rchrdwlihiq
Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches
[article]
2020
IACR Cryptology ePrint Archive
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Hardware implementations of cryptographic operations may quite easily outperform software implementations for at least a subset of major performance metrics, such as speed, power consumption, and energy ...
Finally, early implementations provided a baseline for future design space explorations, paving a way to more comprehensive and fairer benchmarking at the later stages of a given cryptographic competition ...
all KEMs on ASIC Technology TSMC 28 nm TSMC 40 nm UMC 65 nm TSMC 40 nm TSMC 28 nm TSMC 40 nm UMC 65 nm Decapsulation Power Energy (mW) (µJ) 24.94 6.65 23.82 6.71 23.74 22.31 5.80 11.46 5.95 12.07 6.88 ...
dblp:journals/iacr/DangFAMNG20
fatcat:l632lw4f6bgixfv2otzmpi7cmm
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
2020
Automatika
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. ...
Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. ...
The architecture was designed using ASIC 65 nm CMOS technology and compared with other conventional S-box techniques. In [6] reconfigurable VLIW processors to process block cipher are presented. ...
doi:10.1080/00051144.2020.1816388
fatcat:zdrtxvnw2zbwzblpeuv2ypd7ta
Parametrized hardware architectures for the Lucas primality test
2011
2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
analysis and a scheduling of the Lucas sequences computation. ...
Our main contributions are a hardware architecture for calculating the Jacobi symbol based on the binary Jacobi algorithm, a pipelined modular add-shift module for calculating the Lucas sequences, a dependencies ...
INTRODUCTION Many public-key cryptographic algorithms require large prime numbers in order to generate a key pair. ...
doi:10.1109/samos.2011.6045453
dblp:conf/samos/MasleLM11
fatcat:7tcs2zjfdjfolpbbpvoufwu6ue
Foundations of Secure Scaling (Dagstuhl Seminar 16342)
2017
Dagstuhl Reports
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
We recognize that scaling is a fundamental force present at every abstraction level in electronic system design. ...
While scaling is generally thought of as beneficial to the resulting implementations, this does not hold for secure electronic design. ...
As a result, the attacker can launch a cache attack by measuring the total time for the encryption. This technique has been used to attack a remote server. ...
doi:10.4230/dagrep.6.8.65
dblp:journals/dagstuhl-reports/BatinaBSS16
fatcat:qya6rznvonbi7pfic7ocbxwkea
« Previous
Showing results 1 — 15 out of 479 results