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FPGA Implementation of On-Chip Network
2018
DJ Journal of Advances in Electronics and Communication Engineering
This paper presents the design of 32 bit UART (Universal Asynchronous Receiver Transmitter) RISC (Reduced Instruction Set Computing) processor with dynamic power management system to minimize power consumption and transmission cost. Coarse grained architecture is suggested due to its innumerable advantages over fine grained architecture. Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the
doi:10.18831/djece.org/2018021001
fatcat:jfgj5g733zbi5mgkfypfzvn6ga