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Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip
2013
IEEE design & test
Preserved Fulltext
Editor's notes: Integration of untrusted third-party IPs into an SoC design is a major challenge in establishing trustworthiness of the entire SoC. ...
This article presents an approach to ensure information flow isolation between trusted and untrusted IP cores. VSwarup Bhunia, Case Western Reserve University ...
Trusted System-on-Chip With Untrusted Components ...
doi:10.1109/mdt.2013.2247457
fatcat:qbug4w4yi5euxk5qurjaxtt3cy
System-level protection and hardware Trojan detection using weighted voting
2014
Journal of Advanced Research
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Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. ...
A B S T R A C T The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. ...
untrusted because an attacker may replace Trojan logic for original ones or inject a Trojan into chip silicon mask. ...
doi:10.1016/j.jare.2013.11.008
pmid:25685518
pmcid:PMC4294753
fatcat:bphwiutomvh57bbgbeh5sjhv6e
Hardware Trojans
2016
ACM Transactions on Design Automation of Electronic Systems
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., malicious modifications or inclusions made by untrusted third parties) pose major security concerns, especially for those integrated circuits (ICs) and systems used in critical applications and cyber ...
We also identify the most critical lessons for those new to the field and suggest a roadmap for future hardware Trojan research. ...
design house
Untrusted
Trusted
Untrusted
G
Untrusted SoC developer with trusted IPs
Trusted
Untrusted
Untrusted
and significantly impact chip performance. ...
doi:10.1145/2906147
fatcat:24ffmzsrnbgkrkjq3ooztg4fbe
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography
2019
Journal of Hardware and Systems Security
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In this paper, we provide a framework for chip-to-chip authentication that can further improve a Split-Chip system by protecting it from attacks that are unique to Split-Chip. ...
Split-Chip is a dual-IC approach that leverages the performance of an untrusted IC and combines it with the guaranties of a trusted IC. ...
Non-critical IP can reside on the trusted or on the untrusted ICs, with different implications for the system performance. ...
doi:10.1007/s41635-019-00080-y
fatcat:spa3vp3q2zhjpfnk3qirks2x24
COMA: Communication and Obfuscation Management Architecture
[article]
2019
arXiv
pre-print
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as a service (for IoT devices), reducing the side channel threats on key management architecture, and providing two new means of secure communication to/from an untrusted chip. ...
COMA addresses three challenges related to the obfuscated circuits: First, it removes the need for the storage of the obfuscation unlock key at the untrusted chip. ...
The trusted chip could be designed once with utmost security for protection and integrity of data. ...
arXiv:1909.00493v1
fatcat:naee66jm4rg6njwn2rgefgap2u
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks
2021
2021 58th ACM/IEEE Design Automation Conference (DAC)
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Register-transfer level (RTL) locking can protect the sensitive IP semantics and are EDA tool-chain agnostic, allowing seamless integration into arbitrary design flows. ...
In this work, we propose to fortify RTL locking to protect against all untrusted entities in the supply chain, including foundry for oracle-less attacks, and test facility and end users for oracle-guided ...
RTL
IP Design
RTL Locking Logic Synthesis Locked
TABLE I: Comparison with prior work Attack Untrusted foundry Untrusted end user TAO [10] SMT [12] ASSURE [11] SAT [7] This work -ICs. ...
doi:10.1109/dac18074.2021.9586314
fatcat:lvudkil7gnf4dpshxoiafy2mbu
Integrity at Every Link: A Roadmap to Trustworthy Hardware Supply Chains
2024
Zenodo
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Ensuring its integrity throughout the entirety of the hardware supply chain poses a significant challenge in establishing a secure computer system. ...
The involvement of numerous untrusted parties in the process opens the door to vulnerabilities. ...
External Design House • The IP owner may collaborate with an external design house for specialized expertise or additional resources. • The IP owner provides either the RTL design or gate-level netlist ...
doi:10.5281/zenodo.10875049
fatcat:7dnc3zecz5h4lmy6ndc67uwpzy
EDA tools trust evaluation through security property proofs
2014
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
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To support the EDA tools evaluation framework, a new gate-level information assurance scheme is developed for security property checking on any gatelevel netlist. ...
The security concerns of EDA tools have long been ignored because IC designers and integrators only focus on their functionality and performance. ...
However, because of the time-to-market pressure and the request to lower design costs, circuit designers and system integrators rely more on third-party IP cores and commercial EDA tools than ever before ...
doi:10.7873/date.2014.260
dblp:conf/date/Jin14
fatcat:iplwejhsqrhuhmsbsubbga7moq
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets
2020
IEEE transactions on computers
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2020 pre-print arXiv:2009.02412v1 fatcat:2gthmjgxkjcpzghz6wwtps5azmOther Versions
Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust. ...
The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. ...
ACKNOWLEDGMENTS This work was supported in part by the Center for Cyber Security at NYU New York/Abu Dhabi (NYU/NYUAD) and by the NYUAD REF scheme under grant RE218. The work of S. ...
doi:10.1109/tc.2020.3020777
fatcat:dgjm5l6kcvf3bdp745qhwr2yt4
Hardware Security in IoT Devices with Emphasis on Hardware Trojans
2019
Journal of Sensor and Actuator Networks
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This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough. ...
These devices must be protected against sophisticated attacks, especially if the groundwork for the attacks is already laid in devices during design or manufacturing process, such as with HTs. ...
B.J.M. was responsible for guiding the hardware security part, helped in the security analysis and writing the paper. ...
doi:10.3390/jsan8030042
fatcat:zuzw6sf2hzgdfiz65p2joz2g6a
Hardware Trojan Attacks: Threat Analysis and Countermeasures
2014
Proceedings of the IEEE
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; or leak secret information from inside a chip to illegally access a secure system. ...
Trojans may be inserted into IPs of different forms by a rogue designer or an untrusted CAD tool in an IP design house. Existing solutions for trusted IP acquisition fall into three broad classes. ...
doi:10.1109/jproc.2014.2334493
fatcat:kxnyfwrk6jgqrmdpga33odvofq
Electronics Supply Chain Integrity Enabled by Blockchain
2019
ACM Transactions on Design Automation of Electronic Systems
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In the past few decades, the security of software running on these systems has received significant attention. ...
With the rapid globalization of the semiconductor industry, it has become challenging to ensure the integrity and security of hardware. ...
vendors to produce a complete system-on-chip (SoC). • Foundry (also called fab) is the fabrication facility that gets the design file (e.g., GDSII format for IC, or Gerber format for PCB) from the IP owner ...
doi:10.1145/3315571
pmid:32116465
pmcid:PMC7047669
fatcat:ppkjxra4c5a73ecnrarrizr2jy
High-level design methods for hardware security
2022
Proceedings of the 59th ACM/IEEE Design Automation Conference
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This significantly limits the application in industrial designs, potentially affecting the security of the resulting chips. ...
Due to the globalization of the electronics supply chain, hardware engineers are increasingly interested in modifying their chip designs to protect their intellectual property (IP) or the privacy of the ...
Karri was supported in part by ONR Award # N00014-18-1-2058, NSF Grant # 1526405, NYU Center for Cybersecurity, and NYUAD Center for Cybersecurity. ...
doi:10.1145/3489517.3530635
fatcat:cmzq3qod5naejgmqdvsnsbsq6u
Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits
2014
2014 IEEE Computer Society Annual Symposium on VLSI
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Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips ...
and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. ...
SECURITY ANALYSIS ON DFT TECHNIQUES The Design-for-Test (DFT) technique was developed along with the development of integrated circuits and is even more important for modern integrated systems where billions ...
doi:10.1109/isvlsi.2014.54
dblp:conf/isvlsi/Jin14
fatcat:t3ub7g7p35hd3izto6ua4e3zxy
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control
[article]
2021
arXiv
pre-print
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Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. ...
In security-critical applications, IP cores have different privilege levels for accessing shared resources, which must be regulated by an access control system. ...
On-chip Access Control Systems This section discusses options for the implementing on-chip access control system. ...
arXiv:2106.13263v1
fatcat:ikwajwmyavgx7pxi64lhob5qfq
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