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RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)
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In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. ...
The heuristic aims at maximi::ing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. ...
In this paper we present a REtiming heuristic for optimal resource utilization with least shared memory utilization of HW/SW CODesigns (RECOD). The paper is organized as follows. ...
doi:10.1109/hsc.1998.666251
fatcat:q4ajv4mqznfulokwizpzzowwna
Hardware-software partitioning and pipelined scheduling of transformative applications
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The scheduler uses a novel retiming heuristic that optimizes the initiation interval, number of pipeline stages, and memory requirements of the particular design alternative. ...
The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. ...
RECOD optimizes the initiation interval, pipeline buffers, and number of pipeline stages of a pipelined HW-SW codesign. ...
doi:10.1109/tvlsi.2002.1043323
fatcat:5piedlpp6vgv3jvfhdjkl7cbfi
Performance evaluation tool for rapid prototyping of hardware-software codesigns
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)
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A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2004; you can also visit the original URL.
The file type is application/pdf.
During design space exploration the tool obtains performance estimates by using well known scheduling and novel retiming heuristics. ...
In contrast to co-simulation and static analysis, the tool is able to provide fast and accurate performance estimates. ...
The performance evaluation tool uses RECOD 5 which optimizes the resource and memory utilization of HW SW codesigns. A brief explanation of the heuristics is as follows. ...
doi:10.1109/iwrsp.1998.676695
dblp:conf/rsp/ChathaV98
fatcat:ej33bhihnvblbawbtvuyqascei