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Power Analysis of an FPGA
[chapter]
2004
Lecture Notes in Computer Science
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In this paper we investigate the vulnerability of Rijndael FPGA (Field Programmable Gate Array) implementations to power analysis attacks. ...
Then, we propose theoretical predictions of the attacks that we confirmed experimentally, which are the first successful experiments against an FPGA implementation of Rijndael. ...
against an FPGA implementation of Rijndael is divided into three steps. ...
doi:10.1007/978-3-540-28632-5_3
fatcat:lnjvsb22x5etpap2iobvutpl4e
FPGA Implementations of SPRING
[chapter]
2014
Lecture Notes in Computer Science
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Our first (pragmatic) contribution is the first FPGA implementation of SPRING in a counter-like mode. ...
Yet, we argue that for this second part of the design, resistance against "simple power analysis" may be sufficient to obtain concrete implementation security. ...
Note that n is a power of 2, and any BCH code over GF (2) is of length 2 t − 1 for some integer t. To make the matrix compatible with an n that is a power of two, the extended-BCH code can be used. ...
doi:10.1007/978-3-662-44709-3_23
fatcat:fsopd5ytffbntozwcj7xmq4jiu
First-order DPA Vulnerability of Rijndael: Security and Area-delay Optimization Trade-off
2013
International Journal of Network Security
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We have demonstrated that our approach indeed prevents the first order DPA attack of the Rijndael circuit implemented on FPGA. ...
Masking is a very well known approach as a DPA countermeasure. Due to cascading architecture of masked multiplier, the existing masking schemes increase timing and area complexity. ...
Acknowledgements We are grateful to the Department of Information Technology (DIT), Govt. of India for funding us to fulfil this work. ...
dblp:journals/ijnsec/AlamGCS13
fatcat:x6kxefbnmjbdljjeal7cxfaxq4
An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays
2006
Proceedings of the IEEE
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In particular, Field Programmable Gate Arrays are attractive options for hardware implementation of encryption algorithms, but their security against power analysis is a serious concern, as we discuss ...
the cost and security of different possible countermeasures. ...
It is notably demonstrated that pipelining a loop implementation does not provide an effective countermeasure if an attacker has access to the design details because most of the registers in the pipeline ...
doi:10.1109/jproc.2005.862437
fatcat:6idhtqy76nemrbpeesvd4swheq
Security on FPGAs
2004
ACM Transactions on Embedded Computing Systems
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., the specific curve of an ECC system), and so on. Generally speaking, the more specific an algorithm is implemented the more efficient it can become. ...
This contribution provides a state-of-the-art description of security issues on FPGAs, both from the system and implementation perspectives. ...
In [Kocher et al. 1999] two practical attacks, Simple Power Analysis (SPA) and Differential Power Analysis (DPA) were introduced. ...
doi:10.1145/1015047.1015052
fatcat:h3tdckulvnhf7puph5iotxt6pa
Analysis and Improvements of the DPA Contest v4 Implementation
[chapter]
2014
Lecture Notes in Computer Science
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DPA Contest is an international framework which allows researchers to compare their attacks under a common setting. ...
The latest version of DPA Contest proposes a software implementation of AES-256 protected with a low-entropy masking scheme. ...
Acknowledgments Authors are grateful to Guillaume Duc for the animation of the DPA contests, and to all the DPA contest participants, who made these competitions live and very active. ...
doi:10.1007/978-3-319-12060-7_14
fatcat:qoasjvfyjfallhggkh5kmrw6di
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
[chapter]
2005
Lecture Notes in Computer Science
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Under exactly the same hypotheses as in a Differential Power Analysis (DPA), we describe an improvement of the previously introduced higherorder techniques allowing us to defeat masked implementations ...
The proposed technique is based on the efficient use of the statistical distributions of the power consumption in an actual design. ...
Acknowledgements.The authors would like to thank Cédric Archambeau for useful comments on previous versions of this paper. ...
doi:10.1007/11545262_23
fatcat:vkd5wt4fpfcf7f7cq5smpiv4he
Pushing the Limits: A Very Compact and a Threshold Implementation of AES
[chapter]
2011
Lecture Notes in Computer Science
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Our contribution is twofold: first we describe a very compact hardware implementation of AES-128, which requires only 2400 GE. ...
Then we apply the threshold countermeasure by Nikova et al. to the AES S-box and yield an implementation of the AES improving the level of resistance against first-order side-channel attacks. ...
Acknowledgment The authors would like to thank Akashi Satoh and Research Center for Information Security (RCIS) of Japan for the prompt and kind help in obtaining SASEBOs, and François-Xavier Standaert ...
doi:10.1007/978-3-642-20465-4_6
fatcat:ozdax4u4nnhfzi4qj6ukeojxqm
A Survey of Recent Results in FPGA Security and Intellectual Property Protection
[chapter]
2013
Secure Smart Embedded Devices, Platforms and Applications
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Progresses over the last 10 years have improved their capabilities to the point where they can hold a complete System on a Chip (SoC) and thus become an attractive platform for an increasing number of ...
The chapter is structured in three main sections. First, we briefly describe the structure of recent FPGAs. ...
Among the different types of power-based attacks available in literature, the most common ones are Simple Power Analysis (SPA) and Differential Power Analysis (DPA). ...
doi:10.1007/978-1-4614-7915-4_9
fatcat:bp2upohaffe4nl5qlx3gykrncm
A Defense Mechanism for Differential Power Analysis Attack in AES
2015
Journal of Computer Science
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The proposed design is implemented in Vertex III FPGA device and found even after 17230 power traces the secret key is not disclosed as the power fluctuations is completely random. ...
The power consumption when experimented by micro wind software proves to be constant and the same power (almost) is obtained while implementing it hardware and no chance of identifying the instant of data ...
Ethics This article is original and contains unpublished material. The corresponding author confirms that all of the other authors have read and approved the manuscript and no ethical issues involved. ...
doi:10.3844/jcssp.2015.291.296
fatcat:uddctpb74zfphcrc4bebmodutq
A Survey on Advanced Encryption Standard
2017
International Journal of Science and Research (IJSR)
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AES is based on substitution-permutation strategy. It is accepted by NIST in 2001 after the five year of security evaluation. ...
This paper depicts all the valuable work done on the Advanced Encryption Standard since it is accepted by National Institute of Standards and Technology (NIST). ...
By means of power analysis, normal AES is broken in 1999 [56] . To protect the data from differential power analysis (DPA) attacks, a high throughput masked AES is projected [57] . ...
doi:10.21275/art20164149
fatcat:37j5ensjfrhyhabd5kdedzrquq
Spin Me Right Round Rotational Symmetry for FPGA-Specific AES
2018
Transactions on Cryptographic Hardware and Embedded Systems
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A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs. ...
In contrast, a naïve implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). ...
Lauren De Meyer is funded by a PhD fellowship of the Fund for Scientific Research -Flanders (FWO). ...
doi:10.13154/tches.v2018.i3.596-626
dblp:journals/tches/Meyer0W18
fatcat:fgjc6kzmbrf4pd2t2igce2yvce
Low energy security optimization in embedded cryptographic systems
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
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In particular a model for key masking with the objective of minimizing energy overhead is presented. ...
With the emergence of security applications in PDAs, cell phones, line card accelerators, etc, optimizing low energy countermeasures for resistance to power/ electromagnetic attacks is crucial for supporting ...
A second order is required since the power sample of the mask and the power sample of the XOR result are used (in an n th order DPA n power samples are required). ...
doi:10.1145/1016720.1016774
dblp:conf/codes/Gebotys04
fatcat:fv4dxenccjaq5eowcgk6unwuhu
Buying AES Design Resistance with Speed and Energy
[chapter]
2016
Lecture Notes in Computer Science
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Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. ...
We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user's needs and the system's constraints. ...
A full study of this solution would require an ASIC implementation with real tri-state buffers, as an FPGA emulates these buffers and may turn out to be resistant because of an undesired CLB mapping side ...
doi:10.1007/978-3-662-49301-4_9
fatcat:wwupxeiadvblthqm6n5lbn7hvy
Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks
2004
Journal of Integrated Circuits and Systems
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Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. ...
Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance ...
Moreover, from a security point of view, since the side-channel attacks were discovered, the implementations of the cryptographic algorithms are particularly vulnerable against Differential Power Analysis ...
doi:10.29292/jics.v1i1.249
fatcat:5wkdpe4yrbdxhp6kelxvfhadge
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