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A review of high-level synthesis for dynamically reconfigurable FPGAs
2000
Microprocessors and microsystems
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The differences in high-level synthesis technology between classical systems and dynamically reconfigurable systems are discussed. ...
In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. ...
The SPARCS system contains a temporal partitioning tool to divide and schedule temporally the tasks on the reconfigurable architecture, and a spatial partitioning tool to map the tasks to individual FPGAs ...
doi:10.1016/s0141-9331(00)00074-0
fatcat:j2udiqvfvja3xieopntaquluce
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system
2003
Microprocessors and microsystems
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In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. ...
Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. ...
Previous advanced works in the field of temporal partitioning and synthesis for RTR architecture [12 -19] focus on application development approach targeting already designed reconfigurable architecture ...
doi:10.1016/s0141-9331(02)00102-3
fatcat:tnnea26libehflckxqrkfrftmi
Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)
2007
it - Information Technology
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This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level ...
Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes. ...
To conclude, we partition by referring to spacial (spectral method) and temporal (temporal algorithm) information. ...
doi:10.1524/itit.2007.49.3.149
fatcat:gaabsiltkzhq3h54wcou2qw6he
Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. ...
The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. ...
In an earlier work [8] , we presented a mathematical model for combined temporal partitioning and operation level synthesis. ...
doi:10.1145/307418.307490
fatcat:z5uborw4pvhn7idgnbcy7fbbsa
An Enhanced Network Flow Algorithm for Temporal Partitioning into Reconfigurable Architectures
2015
Journal of Computers
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His research interests include high level synthesis, methodologies development for reconfigurable architectures. ...
His research interests include high level synthesis, methodologies development for reconfigurable architectures. ...
We are grateful to our Dean Dean Mr Youssef Ahmad AL-JASSER for his motivation. ...
doi:10.17706/jcp.10.3.176-183
fatcat:gv3h5reycvddle6bf55erccftq
OaaS Based on Temporal Partitioning with Minimum Energy Consumption
2016
Procedia Computer Science
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As a solution for these challenges, we propose to use Workflow partitioning technique and this based on temporal dynamic reconfiguration approach. ...
The proposed approach is based on two main steps: 1) Estimate the energy consumption of BPEL processes 2) Temporal and dynamic partitioning of BPEL process based on reconfigurable architecture in order ...
The Temporal Reconfiguration Approach The temporal partitioning problem based on reconfigurable architectures deserves more attention in reconfigurable computing. ...
doi:10.1016/j.procs.2016.08.232
fatcat:axat4r7ev5bitol3tcpzu3agky
A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs
2001
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Index Terms-DRFPGA, dynamically reconfigurable FPGA, FIPSOC, temporal bipartitioning. ...
The method is based on a temporal bipartitioning technique that is able to separate the static implementation of a circuit in two temporal independence hardware contexts. ...
Example 2, BSAT, enables us to quickly explore architectures and algorithms for solving Boolean satisfiability problems on FPGAs. ...
doi:10.1109/92.920836
fatcat:nuesq2iucndfxbyo653qlej5y4
Runtime Adaptive Extensible Embedded Processors — A Survey
[chapter]
2009
Lecture Notes in Computer Science
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In this article, we provide a detailed survey of the contemporary architectures that offer such dynamic instruction-set support and discuss compiler and/or runtime techniques to exploit such architectures ...
and flexibility. ...
Architecture Temporal Reconfiguration. We start with architectures that enable temporal reconfiguration, but only one custom instruction can exist at any point of time. ...
doi:10.1007/978-3-642-03138-0_23
fatcat:dmhl3mmoxrhfhhcanrryjt5tum
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration
2006
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06
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Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. ...
In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. ...
ACKNOWLEDGEMENTS This research is partially supported by the Brazil agencies: CNPq and FACEPE. ...
doi:10.1145/1150343.1150361
dblp:conf/sbcci/NascimentoLSS06
fatcat:5cqburfnozbkdfai42sphpp3vm
Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration
2007
Journal of Integrated Circuits and Systems
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Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. ...
In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. ...
ACKNOWLEDGEMENTS This research is partially supported by the Brazil agencies: CNPq and FACEPE. ...
doi:10.29292/jics.v2i1.235
fatcat:2tbyedo3jvdn5ptgmasdqn3hxe
Hardware-software co-design of embedded reconfigurable architectures
2000
Proceedings of the 37th conference on Design automation - DAC '00
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In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath ...
The partitioning algorithm optimizes the global application execution time, including the software and hardware execution times, communication time and datapath reconfiguration time. ...
For dynamically reconfigurable architectures, besides spatial partitioning, the partitioning algorithm needs to perform temporal partitioning, meaning that the FPGA can be reconfigured at various phases ...
doi:10.1145/337292.337559
dblp:conf/dac/LiCDHKS00
fatcat:b6ld6t5i2bajrk755nlhoop2pq
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures
2007
IEICE transactions on information and systems
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Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. ...
Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. ...
These benchmark suites have been used widely for evaluating various architectures and software optimizations such as partitioning and compilers. ...
doi:10.1093/ietisy/e90-d.12.1977
fatcat:l7zkqoe42zd4ncdxra32iu6dhq
A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems
2003
EURASIP Journal on Advances in Signal Processing
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Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. ...
We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. ...
Previous advanced works exist in the field of temporal partitioning and synthesis for RTR architectures [9, 10, 11, 12, 13, 14] . All these approaches assume the existence of a resources constraint. ...
doi:10.1155/s1110865703212051
fatcat:swehivaq3zfwhnznmgu53jq3ku
CHARSTAR
2017
SIGARCH Computer Architecture News
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The CHARSTAR design is further optimized for balanced spatiotemporal reconfiguration and also enables efficient joint control of resource and frequency scaling. ...
The primary contribution of CHARSTAR is optimizing reconfiguration mechanisms to become clock hierarchy aware. ...
ACKNOWLEDGEMENTS The authors would like to thank anonymous reviewers for their insights and comments, Essan Swain for relevant CRIB RTL design and Michael Mishkin for CRIB topology generation, all of which ...
doi:10.1145/3140659.3080212
fatcat:wylho4k46ffcxdm65xf4lrjvla
An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
2006
Journal of Computer Science
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In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. ...
The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints. ...
The system contains a temporal partitioning tool, a spatial partitioning tool, and a high-level synthesis tool. ...
doi:10.3844/jcssp.2006.422.430
fatcat:acs2dvanxjgiriqk66svqtwcza
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