Exploiting FPGA block memories for protected cryptographic implementations.

This chapter discusses how the specificities of Field Programmable Gate Arrays (FPGAs) can be exploited for the secure and efficient implementation of symmetric cryptographic algorithms and protocols. ... Acknowledgements: The author would like to thank Fraçois Macé, Guerric Meurice and Gaël Rouvroy for meaningful comments on this work. ... Second, micro-controllers can be synthesized and implemented within the FPGA logic blocks, just as distributed memories. ...

doi:10.1007/978-0-387-71817-0_11 fatcat:bn7exzl3mffm5k2f6f3v5firfy

Our goal is to evaluate the suitability of the aforementioned algorithms for FPGA-based implementations. ... Our results suggest that Rijndael and Serpent favor FPGA implementations the most since their algorithmic characteristics match extremely well with the hardware characteristics of FPGAs. ... To implement efficient key-setup circuits, we took advantage of the embedded memory modules (Block SelectRAM) of the Virtex FPGAs [16] . ...

doi:10.1007/3-540-44499-8_9 fatcat:qcwvolwjr5g63ne7mrwzwepjpe

for runtime protection. ... This work proposes a full boot-to-runtime protection flow of an embedded Linux kernel during boot and confidentiality/integrity protection of the external memory containing the kernel and the main application ... Security Policy memory layout for Local and Cryptographic Firewalls BRAMs data ports are 32-bit wide, a Security Policy for a LF is read in 1 clock cycle instead of 6 cycles for a Cryptographic Firewall ...

doi:10.1109/recosoc.2012.6322896 dblp:conf/recosoc/CotretDGBT12 fatcat:c2jcn5rsifeq3ogbo4bnqpi4ue

Fine grain reconfigurable architectures like FPGAs are providing many interesting features to be selected as an efficient target for embedded systems when security is an important concern. ... We identify the main vulnerabilities of FPGAs to tackle the security requirements based on the security pyramid concept. ... For such a model, in addition to protecting the I/O interfaces with the system as a whole, it is necessary to protect the communication inside the system in a per-block (Memory, Processor, FPGA) granularity ...

doi:10.1007/978-94-007-1338-3_2 fatcat:5iqydsjq4nhbho63ccanv5csxa

These firewalls filter all data going through the system communication bus and an additional flexible cryptographic block aims to protect external memory from attacks. ... To illustrate the benefit of such a solution, implementations are discussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. ... Given the fact that console developers are able to implement their architectures on a FPGA chip, the solution described in this work is an efficient solution to block malicious exploits at both hardware ...

doi:10.1016/j.micpro.2016.01.013 fatcat:wnqzdr46qvcudc4vcvkf354ray

Multiple Versions

To solve this issue, we present an open-source framework for building transparent RAM encryption and authentication pipelines, suitable for both FPGAs and ASICs. ... Moreover, the use of a cryptographically strong primitive like Ascon yields highly practical results with 54 % bandwidth utilization. ... The cipher blocks only have to support encryption/decryption of memory requests with alignment and block size appropriate for the respective primitive, which greatly reduces implementation complexity. ...

doi:10.23919/fpl.2017.8056797 dblp:conf/fpl/WernerUSSM17 fatcat:3ul2nslkqve4dc3ewfnnptvflm

In this work we present an architecture for software protection that provides for a high level of both security and user transparency by utilizing field programmable gate array (FPGA) technology as the ... We demonstrate that by relying on FPGA technology, this approach can accelerate the execution of programs in a cryptographic environment, while maintaining the flexibility through reprogramming to carry ... FPGA implementations of symmetric block often strive to optimize for either throughput or area. ...

doi:10.1109/jproc.2005.862474 fatcat:amcriqendfghhhznonhwqzs4qq

Finally, we emphasize recent trends for improving IP security in FPGAs, including bitstream security, the use of code watermarking techniques and the exploitation of Physically Unclonable Functions (PUFs ... Second, how can we guarantee that the IP corresponding to FPGA designs is protected (i.e. cannot be easily counterfeited)? ... Specific features of state of the art FPGAs were also exploited for implementing masking: the larger input size of the basic block of Xilinx Virtex-5 FPGA was combined with optimization techniques for ...

doi:10.1007/978-1-4614-7915-4_9 fatcat:bp2upohaffe4nl5qlx3gykrncm

In order to validate our approach we implemented a lightweight architecture of AES in the Partial Separated Dynamic Differential Logic (Partial SDDL) for FPGAs. ... We propose principle rules for Partial DDL to guide the designer in how to split up a circuit into DDL protected and unprotected paths. ... Principle Rules for Partial DDL We propose the following principle rules for implementing Partial DDL on cryptographic implementations: • The cryptographic implementations should be thoroughly analyzed ...

doi:10.1109/fccm.2010.49 dblp:conf/fccm/KapsV10 fatcat:m2ckxao34fesdedkgkttrghzby

The proposed solution perfectly fits embedded devices that are nowadays commonly equipped with reconfigurable hardware components exploited for solving different computational problems. ... This paper proposes the use of reconfigurable computing to build a consistent architecture for generating attestations (proofs) of code integrity for an executing program, and for delivering them to the ... It computes code integrity attestations for P exploiting the direct link between the FPGA and the system's memory (DMA in Fig. 1 ). ...

doi:10.1109/tsmcc.2011.2106493 fatcat:7sbaap5yarhplci7kentk42qhq

For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key ... block ciphers, stream ciphers, and hash functions). ... ., the number of blocks) to be encrypted and exploits the parallelism available in GPUs. ...

doi:10.1145/2501654.2501655 fatcat:h5pccigb35hfvinkrpn7s75gl4

Second, we demonstrate automatic injection of hardware Trojans specifically tailored for third-party cryptographic IP gate-level netlists. ... More precisely, we extend our understanding of adversary's capabilities by presenting how block and stream cipher implementations can be surreptitiously weakened. ... The high-level idea of the scheme by Schmid et al. is to exploit not addressable LUT memory space, see Fig. 1 . ...

doi:10.1109/ivsw.2017.8031551 dblp:conf/ivsw/WallatFSP17 fatcat:dyluub4lbzakjlmyk445dfibk4

Multiple Versions

The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. ... Even though there have been many contributions dealing with the algorithmic aspects of cryptographic schemes implemented on FPGAs, this contribution appears to be the first comprehensive treatment of system ... Note that the listed potential advantages of FPGAs for cryptographic applications can only be exploited if the security shortcomings of FPGAs discussed in the following have been addressed. ...

doi:10.1007/978-3-540-45234-8_10 fatcat:2uvfoqvdmjcj5h7572rvztoivi

This paper proposes a joint compiler/hardware infrastructure -CODESSEAL -for software protection for fully encrypted execution in which both program and data are in encrypted form in memory. ... Software protection, particularly for security applications, has become an important area in computer security. ... (Ongoing work explores the use of other cryptographic algorithms.) The hashes are stored in each block as well as in the FPGA. The FPGA performs hash verification as each block loads. ...

doi:10.1007/11427995_54 fatcat:2kqmjapwdrhibcbjegfcgt4uq4

The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows. 978-3-9815370-0-0/DATE13/ c 2013 EDAA ... The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical ... Fig. 5 . 5 Security experiments for AES-128 hardware implementation on a Xilinx Virtex-5 FPGA. ...

doi:10.7873/date.2013.093 dblp:conf/date/BayrakVRNBI13 fatcat:zkfzecxvcfhvrdqdnwflmpu6cu

Secure and Efficient Implementation of Symmetric Encryption Schemes using FPGAs [chapter]

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A Comparative Study of Performance of AES Final Candidates Using FPGAs [chapter]

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Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system

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Security FPGA Analysis [chapter]

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Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

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Transparent memory encryption and authentication

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High-Performance Software Protection Using Reconfigurable Architectures

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A Survey of Recent Results in FPGA Security and Intellectual Property Protection [chapter]

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DPA Resistant AES on FPGA Using Partial DDL

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FPGA-Based Remote-Code Integrity Verification of Programs in Distributed Embedded Systems

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Architectures of flexible symmetric key crypto engines—a survey

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A look at the dark side of hardware reverse engineering - a case study

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How Secure Are FPGAs in Cryptographic Applications? [chapter]

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CODESSEAL: Compiler/FPGA Approach to Secure Applications [chapter]

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An EDA-Friendly Protection Scheme against Side-Channel Attacks

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