A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
DPA Resistant AES on FPGA Using Partial DDL
2010
2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Current techniques to implement Dynamic Differential Logic (DDL), a countermeasure against Differential Power Analysis (DPA) on Field Programmable Gate Arrays (FPGAs) lead to an increase in area consumption of up to factor 11. In this paper we introduce Partial DDL, a technique in which DDL is applied only to a part of the cryptographic hardware implementation. We propose principle rules for Partial DDL to guide the designer in how to split up a circuit into DDL protected and unprotected paths.
doi:10.1109/fccm.2010.49
dblp:conf/fccm/KapsV10
fatcat:m2ckxao34fesdedkgkttrghzby