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An energy-efficient data cache with byte-repeat pattern encoding
2008
IEICE Electronics Express
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Several data compression techniques including Frequent Value Caches are proposed to reduce the energy consumption in the data cache memories. ...
These values can be represented with one byte and the pattern type bits. We propose a new energy-efficient data cache, the Byte-Repeat Pattern Cache, which employs this encoding scheme. ...
In this paper, we present a new energy-efficient data cache, which is a Byte-Repeat Pattern Cache (BRPC) with a new data encoding technique. ...
doi:10.1587/elex.5.833
fatcat:hgdpihleejdqhokuba7qlq4cie
Row buffer locality aware caching policies for hybrid memories
2012
2012 IEEE 30th International Conference on Computer Design (ICCD)
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We propose a new caching policy that improves hybrid memory performance and energy efficiency. ...
Compared to a conventional DRAM-PCM hybrid memory system, our row buffer locality-aware caching policy improves system performance by 14% and energy efficiency by 10% on data-intensive server and cloud-type ...
Compared to a conventional caching policy that places frequently accessed data in DRAM (oblivious of row buffer locality), our scheme improves system performance by 14% and energy efficiency by 10%. ...
doi:10.1109/iccd.2012.6378661
dblp:conf/iccd/YoonMAHM12
fatcat:h6kyo3hs5zdc5caruau3xzuyy4
Power Efficient Instruction Caches for Embedded Systems
[chapter]
2005
Lecture Notes in Computer Science
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Unlike loop caches, K-store maps the frequent code in a reserved address space and hence, it can switch between the kernel memory and the instruction cache without any noticeable performance penalty. ...
We compare the performance and energy consumption of our K-store with that of a conventional instruction cache of equal size. ...
In spite of the higher cost associated with this design, the number of off-chip accesses would be much lesser than that of the baseline cache and hence, this design should be highly energy-efficient. ...
doi:10.1007/11512622_20
fatcat:q7cdw3jaqvcofcktvvpu7ehuku
A survey of architectural techniques for improving cache power efficiency
2014
Sustainable Computing: Informatics and Systems
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Yang and Gupta [46] discuss a 'frequent value' data cache design, which divides the data cache into two arrays. ...
A few techniques provision accessing frequent (hot) data with lower energy to reduce average dynamic energy of cache access [21] , [46] . ...
doi:10.1016/j.suscom.2013.11.001
fatcat:ovbeupgvizabdiubjzqta7mpba
An efficient direct mapped instruction cache for application-specific embedded systems
2005
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05
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We design an efficient cache -a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more efficiently ...
energy savings of 30% compared with a conventional two-way set associative cache. ...
Compared with our efficient cache, Peir's design maps cache sets to less frequently used cache sets to reduce conflict miss in a direct-mapped cache and thus requires a complex design, such as to distinguish ...
doi:10.1145/1084834.1084850
dblp:conf/codes/Zhang05
fatcat:yx5la2qdaref7e4khjy2hciw3y
Practical Data Compression for Modern Memory Hierarchies
[article]
2016
arXiv
pre-print
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We demonstrate that any compression algorithm can be adapted to fit the requirements of LCP, and that LCP can be efficiently integrated with the existing cache compression designs, avoiding extra compression ...
BDI exploits the existing low dynamic range of values present in many cache lines to compress them to smaller sizes using Base+Delta encoding. ...
Energy Efficient Encoding Schemes. Data Bus Inversion (DBI) is an encoding technique proposed to enable energy efficient data communication. ...
arXiv:1609.02067v1
fatcat:i4z7m2ydtjgwvlwmglno26nb54
Cooperative Energy Efficient Management Scheme for Multimedia Information Dissemination
2014
International Journal of Distributed Sensor Networks
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In this paper, we cope with the energy efficient management problem in such network, in which both transmission energy and caching energy are considered. ...
Because of the limited energy in each sensor node, energy efficiency problem is crucial to be considered in information centric sensor network. ...
When caching probability is small, the caching energy is small, but the data objects are obtained with larger hops, leading to higher value of transmission energy. ...
doi:10.1155/2014/718403
fatcat:cbj6xc2lhbecddc63v4cjincbe
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags
2013
International Symposium on Quality Electronic Design (ISQED)
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The proposed design appends additional flags in cache tag arrays and set these additional bits if the corresponding data in the cache line is the zero-valued data in which all data bits are zero. ...
However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. ...
Acknow ledgment This work was supported by The Ministry of Economy, Trade and Industry (METI), and The New Energy and Industrial Technology Development Organization (NEDO). ...
doi:10.1109/isqed.2013.6523613
dblp:conf/isqed/JungNYK13
fatcat:smaik2il5zc7birkbodrrtctty
A survey of power management techniques for phase change memory
2016
International Journal of Computer Aided Engineering and Technology
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A crucial bottleneck in wide-spread adoption of PCM, however, is that its write latency and energy are very high. ...
Since PCM (phase change memory) provides high-density, good scalability and non-volatile data storage, it has received significant amount of attention in recent years. ...
They observe that a large last level cache (LLC) designed with PCM can improve energy efficiency by reducing the costly off-chip accesses. ...
doi:10.1504/ijcaet.2016.10000092
fatcat:gnowq3m4jvfuhbqx2jhc27y27m
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems
2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16
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However, energy harvesting powered embedded systems suffer from frequent execution interruption due to unstable energy supply. ...
In this paper, we will propose replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently. ...
However, all existing hybrid cache architectures and policies are designed for energy efficiency and performance purposes. ...
doi:10.1145/2968456.2968477
dblp:conf/codes/XieZPLLZXH16
fatcat:x2dt26dodra6neq6sxvtsyhbzm
An Efficient STT-RAM Last Level Cache Architecture for GPUs
2014
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14
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They have however two important issues, high energy and latency of write operations, that have to be addressed. Low data retention time STT-RAMs can reduce the energy and delay of write operations. ...
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. ...
is modified for better energy efficiency. ...
doi:10.1145/2593069.2593086
dblp:conf/dac/SamavatianAAS14
fatcat:k5tdiszs5bbflgwgpnove4jj4i
Energy Saving Techniques for Phase Change Memory (PCM)
[article]
2013
arXiv
pre-print
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The aim of this work is encourage researchers to propose even better techniques for improving energy efficiency of PCM based main memory. ...
In recent years, the energy consumption of computing systems has increased and a large fraction of this energy is consumed in main memory. ...
They observe that a large last level cache (LLC) designed with PCM can improve energy efficiency by reducing the costly off-chip accesses. ...
arXiv:1309.3785v1
fatcat:w4ehvlzitjgfnkhzlals3abvoq
An Adaptive Various-Width Data Cache for Low Power Design
2011
IEICE transactions on information and systems
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In view of these observations, this paper proposes an Adaptive Various-width Data Cache (AVDC) to reduce the power consumption in a cache, which exploits the popularity of narrow-width value stored in ...
In fact, many values in a processor rarely need the full-bit dynamic range supported by a cache. The narrow-width value occupies a large portion of the cache access and storage. ...
Furthermore, a low-power reconfigurable data design based on locality and frequent value locality was investigated. ...
doi:10.1587/transinf.e94.d.1539
fatcat:lcldexpcm5acrmicuclmmk7eme
Dynamic Dictionary-Based Data Compression for Level-1 Caches
[chapter]
2006
Lecture Notes in Computer Science
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In this paper, we propose the first dynamic dictionary-based compression mechanism for L1 data caches. ...
Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
The reduction in energy comes at a cost of an additional cycle needed to access non-frequent values. Thus, the PA-DFVC design trades power for performance. ...
doi:10.1007/11682127_9
fatcat:pzq6jppbcbdzdftpsbtwwf7ofi
In-Network Caching for the Green Internet of Things
2021
IEEE Access
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By caching multiple copies of the sensed data and suppressing repeated content deliveries from the sensor nodes, the in-network caching exhibits strong potentials to reduce energy consumption and avoid ...
Since in-network caching is not the optimal choice in some cases, we propose the dynamic in-network caching scheme to decide whether the sensed data should be cached in brokers or not, where the location ...
CASE STUDY In this section, we show the simulation results of the case study designed for the proposed energy-efficient in-network caching scheme in the IoT scenario. ...
doi:10.1109/access.2021.3082532
fatcat:doxyxcmsg5eqbj5tytflp4wte4
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