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Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. ...
A temporal partitioning algorithm is proposed which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. ...
We attempt to use benefits of our greedy temporal partitioning approach in physical design process to achieve better performance in a reconfigurable system. ...
doi:10.1109/ipdps.2006.1639611
dblp:conf/ipps/MehdipourZASM06
fatcat:fznimtjxmzc63hyibcbpdvg5py
Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. ...
Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. ...
However, for a temporal partitioning system increasing the number of partitions increases the area available for the design, but this increase is 'over time' and not 'over space'. ...
doi:10.1145/307418.307490
fatcat:z5uborw4pvhn7idgnbcy7fbbsa
Power-performance trade-offs for reconfigurable computing
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
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In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. ...
However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. This work presents a configurationaware data size partitioning approach. ...
On the other hand, the approach based on HW/SW partitioning for statically reconfigurable architectures, processes small blocks of data that can be stored in on-chip memory resources, which means that ...
doi:10.1145/1016720.1016751
dblp:conf/codes/NogueraB04
fatcat:kmujsufot5gzxnejo72so72t4y
An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
2006
Journal of Computer Science
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In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. ...
The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints. ...
Design space exploration of tasks does not concern the operators level. The first step in our method is the Static Estimation (SE). ...
doi:10.3844/jcssp.2006.422.430
fatcat:acs2dvanxjgiriqk66svqtwcza
A review of high-level synthesis for dynamically reconfigurable FPGAs
2000
Microprocessors and microsystems
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In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. ...
DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. ...
A scheduling and temporal partitioning algorithm for dynamically reconfigurable systems based on a DFG model has been reported in Refs. ...
doi:10.1016/s0141-9331(00)00074-0
fatcat:j2udiqvfvja3xieopntaquluce
Integrated block-processing and design-space exploration in temporal partitioning for RTR architectures
[chapter]
1999
Lecture Notes in Computer Science
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Block-processing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. ...
We propose block-processing in the temporal partitioning framework for reducing the recon guration overhead for partitioned designs. ...
Integrating Design-Space Exploration and Block-Processing in Temporal Partitioning : For FPGA based architectural synthesis, the constraints of area in terms of CLBs Con gurable Logic Blocks FGs Function ...
doi:10.1007/bfb0097945
fatcat:dsjcll5jczcmni27xuxycca4nm
Hardware/software codesign: a systematic approach targeting data-intensive applications
2005
IEEE Signal Processing Magazine
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For example, partitioning in [1] has to be done manually and there is no reconfiguration at run-time. ...
The codesign system is based on the UltraSONIC reconfigurable platform, a system designed jointly at Imperial College and the SONY Broadcast Laboratory. ...
His research interests include VLSI architectures for DSP and video processing, reconfigurable computing, embedded systems, and high-level synthesis and optimization of digital systems, particularly those ...
doi:10.1109/msp.2005.1425894
fatcat:yirzlrhinjepre7olkgcufkqdm
Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study
2008
EURASIP Journal on Embedded Systems
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New reconfigurable technologies and technology-dependent tools have been developed, but a complete overview of the whole design flow for run-time reconfigurable systems is missing. ...
The results show that using run-time reconfiguration can save over 40% area when compared to a functionally equivalent fixed system and achieve 30 times speedup in processing time when compared to a functionally ...
ACKNOWLEDGMENTS This work was previously supported by the European Commission under the Contract IST-2000-30049 ADRIATIC, and later by Tekes (National Technology Agency of Finland) and VTT under EUREKA ...
doi:10.1155/2008/856756
fatcat:cwmqznktrbgfncsxlo5b2hlc6q
Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs
2021
Journal of Signal Processing Systems
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This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more ...
In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design ...
The designed tools then allow automated exploration of the generated design space in different ways. ...
doi:10.1007/s11265-020-01633-z
fatcat:o6b3y6ejynfupci53mj6dqrye4
Ecoscale: Reconfigurable Computing And Runtime System For Future Exascale Systems
2016
Zenodo
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The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming ...
Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of partitions in a Partitioned Global Address Space (PGAS), or as a set ...
In the top layer a runtime system schedules tasks inside a PGAS partition, provides the MPI primitives for communication between PGAS partitions and decides at run-time which functions of the accelerated ...
doi:10.5281/zenodo.34893
fatcat:ocwfndo4vjei3hqucmndj22xu4
Efficient, Dynamic Multi-task Execution on FPGA-based Computing Systems
2021
IEEE Transactions on Parallel and Distributed Systems
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The resource sharing typically involves partitioning the FPGA space into fix-sized slots. ...
The approach is enabled in the system stack by a corresponding task-based virtualisation model. ...
Multi-task design space exploration (DSE) and use of preemptive scheduling to enable an effective runtime resource allocation based on the size of each coexecuted task, in achieving a high temporal density ...
doi:10.1109/tpds.2021.3101153
fatcat:cpixjpmwx5dwpdgyhss5mxy6oq
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration
2006
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06
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In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the ...
A design flow is shown based on library components that implements typical tasks used in the domain of applications. Figure 1. Design space of each task: Area ×Time pareto curve. ...
An efficient algorithm for design space exploration of task implementations inside temporal partitioning is presented and experiments have been shown. ...
doi:10.1145/1150343.1150361
dblp:conf/sbcci/NascimentoLSS06
fatcat:5cqburfnozbkdfai42sphpp3vm
System-level power-performance tradeoffs for reconfigurable computing
2006
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper, we propose a configuration-aware datapartitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. ...
Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. ...
Contributions of This Work This paper explores the system-level power-performance tradeoffs for fine-grained reconfigurable computing. ...
doi:10.1109/tvlsi.2006.878343
fatcat:2blfbpudnbf7zdhc67uele3fai
Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration
2007
Journal of Integrated Circuits and Systems
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In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the ...
Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. ...
An efficient algorithm for design space exploration of task implementations inside temporal partitioning is presented and experiments have been shown. ...
doi:10.29292/jics.v2i1.235
fatcat:2tbyedo3jvdn5ptgmasdqn3hxe
EPICURE: A partitioning and co-design framework for reconfigurable computing
2006
Microprocessors and microsystems
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iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, iv) a HW/SW partitioning approach that refines the specification ...
context of reconfigurable architectures. ...
Acknowledgment This project was funded in part by a grant from the French ministry of research under the RNTL framework. 8 . ...
doi:10.1016/j.micpro.2006.02.015
fatcat:3axbqhlvcrgchibzpj6e6pheqq
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