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Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
2011
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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for quasi-cyclic LDPC codes. ...
that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. ...
the throughput of a decoder for quasi-cyclic LDPC codes. ...
doi:10.1109/tcsi.2010.2055250
fatcat:2zc7gaotrrdlhl37ul52mp3bhi
FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes
2016
Indian Journal of Science and Technology
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Objective: VLSI implementation of Decoder Architecture for high throughput using LDPC codes. ...
LDPC codes are well-known linear block codes. The computational complexity of LDPC codes is very high as compared to other existing codes like Convolutional codes and Turbo codes. ...
In paper 1, the author focuses on power aware LDPC Decoder architecture and mainly accomplishes Quasi-Cyclic LDPC codes are extensively useful in telecommunication systems. ...
doi:10.17485/ijst/2016/v9i48/97269
fatcat:57fxhee65rfmjfkr2goresfcvi
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design
2013
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Various multilevel schemes, including single-pass configurations (V and ) and two-pass configurations (VV, , V , and V), have been experimented, and the results are shown in Table V . ...
Kaminska, "Oscillation-based test strategy for analog and mixed-signal integrated circuits," indard 1500 compatible oscillation ring test methodology for interconnect delay and crosstalk detection," ...
The proposed decoder architecture based on BC-RS-LDPC codes has a high data throughput of 41 Gb/s and low hardware complexity. ...
doi:10.1109/tvlsi.2012.2210452
fatcat:rbpxkut775eqxndv5whjs4voxu
Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation
2007
IEEE transactions on magnetics
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Furthermore, we develop a QC-LDPC decoder hardware architecture that is well suited to achieving high decoding throughput. ...
By implementing a field-programmable gate array (FPGA)-based simulator, we investigate the performance of randomly constructed high-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes for the ...
Moreover, by improving published decoder architectures, we presented a new decoder architecture that is better suited to achieving high throughput for high rate QC-LDPC codes. ...
doi:10.1109/tmag.2006.888607
fatcat:em2f2dlkcja25m66yylvisyody
Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N
2016
International Journal of VLSI Design & Communication Systems
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Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. ...
for 648 block length and 1/2 code rate. ...
They also proposed Configurable and High-
throughput Architectures for Quasi-Cyclic Low-Density Parity-Check encoder for the WiMAX
(IEEE 802.16e) and the WiFi (IEEE 802.1 In) protocols. ...
doi:10.5121/vlsic.2016.7604
fatcat:xslppi6xkzc3vp6stsjjmdqckm
On using the cyclically-coupled QC-LDPC codes in future SSDs
2016
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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Due to their limitapproaching decoding ability, low-density parity-check (LDPC) codes are seen as one of the most promising substitute for the traditional BCH codes, though implementation barriers remain ...
In our recent work, a co-design of LDPC block codes and their decoder architecture are developed and found suitable to apply to address these barriers with an overall excellence in error rate, complexity ...
QC-LDPC Codes QC-LDPC codes are the sub-class of LDPC codes with quasi-cyclic characteristics. ...
doi:10.1109/apccas.2016.7804048
dblp:conf/apccas/LuSL16
fatcat:fmneszrvmjh67px4v436ilmzxa
FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories
2016
IEEE design & test
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In this work, the error performance of very large block length quasi-cyclic (QC) LDPC codes is evaluated through a high speed FPGA based emulator. ...
A novel algebraic QC-LDPC code of rate 0.96 is also proposed for the 8 KB page size of NAND flash memory and its performance is shown. ...
However, long LDPC codes require a large amount of resource on FPGA for high throughput implementation. ...
doi:10.1109/mdat.2015.2497322
fatcat:qlksk32j4jagbdmwdzj2tyv2cy
Quasi-cyclic Random Projection Code and Hardware Implementation
2013
Communications and Network
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To reduce hardware implementation complexity, we design a quasi-cyclic mapping matrix for RPC codes. ...
Random projection code's mapping matrix has significant influences on decoding performance as well as hardware implementation complexity. ...
[10] has given pipelined hardware implementation architecture of LDPC codes to achieve high data throughput rate. ...
doi:10.4236/cn.2013.53b2017
fatcat:osznbjdf3redvew47lu4wuqjku
Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
2021
Electronics
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This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant ...
Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered ...
Quasi-Cyclic LDPC Codes QC-LDPC codes [29] , which are a class of structured LDPC codes, are widely used in many practical applications. ...
doi:10.3390/electronics10040516
fatcat:lur7ley3kbhi7bzbevn2ih7hnq
Resource Efficient LDPC Decoders for Multimedia Communication
[article]
2013
arXiv
pre-print
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This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. ...
The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix with innovative layering of random sub-matrices ...
It relies on a novel technique to flexibly construct LDPC matrices for different code lengths using a Hierarchical Quasi-Cyclic (HQC) based approach. ...
arXiv:1305.6216v2
fatcat:a7dglh2fcfhcfets2kjggtdt5q
FPGA implementation of advanced FEC schemes for intelligent aggregation networks
2016
Optical Metro Networks and Short-Haul Systems VIII
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While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and lowdensity parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques ...
In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10 -15 in entire code ...
ACKNOWLEDGMENT This work was supported in part by NSF ERC Center for Integrated Access Networks (CIAN) under grant EEC-0812072 as well as by MURI ONR program. ...
doi:10.1117/12.2214884
fatcat:dbrmqmdvbjbj7b6vetnxnlrqda
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units
2016
2016 Euromicro Conference on Digital System Design (DSD)
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In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. ...
Synthesis results targeting a 65nm CMOS technology for a (3, 6)-regular (648, 1296) Quasi-Cyclic LDPC code and for the WiMax (1152, 2304) irregular QC-LDPC code show significant improvements in terms of ...
In Section II we briefly review QC-LDPC codes and the MS decoding algorithm. Section III details the proposed low-cost, high-throughput flexible architecture for the layered MS decoder. ...
doi:10.1109/dsd.2016.33
dblp:conf/dsd/Nguyen-LyGPSDC16
fatcat:hiu4ihkuonfgpjzkl4jdem7f6m
An Automated FPGA-based Framework for Rapid Prototyping of Nonbinary LDPC Codes
[article]
2022
arXiv
pre-print
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We propose a high-throughput reconfigurable hardware emulation architecture with decoder and peripheral co-design. ...
We demonstrate the capability of the framework in evaluating practical code and decoder design by experimenting with two popular nonbinary LDPC codes, regular (2, dc) codes and quasi-cyclic codes: each ...
dc) codes [11] and quasi-cyclic codes [12] . ...
arXiv:2202.07295v2
fatcat:ihd3movalze4hantr33budsasa
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
2006
Signal Processing Systems Design and Implementation (siPS), IEEE Workshop on
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FPGA implementation of our proposed architectures for a (1536, 768) (3, 6)-regular QC LDPC code can achieve an estimated 61 Mbps decoding throughput at SNR= 4.5 dB. ...
Finally, noncoherent OSP decoder, which does not always satisfy the data dependency constraints, is proposed to ensure that the maximum throughput gain 2 of the OSP decoding is achieved for all QC LDPC ...
For LDPC codes with w cv > m 2 , we propose noncoherent OSP (NOSP) decoder so as to achieve high throughput and HUE. ...
doi:10.1109/sips.2006.352585
dblp:conf/sips/ChenDY06
fatcat:a5o2zvzp4zcydenzy4zlbr64lu
A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
2010
2010 IEEE Asian Solid-State Circuits Conference
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We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. ...
The corresponding 90 nm CMOS ASIC has a core area of 1.77 mm 2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. ...
Felber for their support during ASIC design and testing. The presented work was kindly supported by the Hasler Foundation and the Swiss National Science Foundation. ...
doi:10.1109/asscc.2010.5716618
fatcat:opdu5b5lxbhzzbuk27uahk555e
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