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An integrated temporal partitioning and partial reconfiguration technique for design latency improvement
Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)
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In this paper, we present a novel partitioning methodology that temporally partitions a design for such a partially reconfigurable processor and improves design latency by minimizing reconfiguration overhead ...
We have incorporated block-processing in the partitioning framework for reducing reconfiguration overhead of partitioned designs. ...
Concluding Remarks In this paper, we have presented a novel temporal partitioning, and execution and reconfiguration pipelining technique to partition designs for partial RC systems. ...
doi:10.1109/date.2000.840290
dblp:conf/date/GanesanV00a
fatcat:zjsregiwo5gzthaszkkbi5kj4e
An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
2006
Journal of Computer Science
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In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. ...
The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints. ...
A framework for the Design and Implementation of Dynamically and Partially Reconfigurable Systems "PaDReH" is proposed in [10, 11] . ...
doi:10.3844/jcssp.2006.422.430
fatcat:acs2dvanxjgiriqk66svqtwcza
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. ...
An incremental physical design process based on similar configurations produced in the partitioning stage improves the metrics over iterations. ...
SPARCS [9] is an integrated partitioning and synthesis framework which has a temporal partitioning tool to temporally divide and schedule the tasks on a reconfigurable system. ...
doi:10.1109/ipdps.2006.1639611
dblp:conf/ipps/MehdipourZASM06
fatcat:fznimtjxmzc63hyibcbpdvg5py
Special issue: applications, results & future direction (EAIS 12): 2
2014
Evolving Systems
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The last paper of this special issue is ''Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement'' by Ramzi Ayadi, Bouraoui Ouni and Abdellatif Mtibaa. ...
This paper presents a novel temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable systems. ...
doi:10.1007/s12530-014-9111-3
fatcat:5qfgljv5zjahrik5rwiyrtp4tq
Design Partitioning Methodology for Systems on Programmable Chip
2014
International Journal of Electronics and Electrical Engineering
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In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for reconfigurable architecture. ...
In reconfigurable computing systems, are evolving rapidly, due to their flexibility and high performance. ...
This can be accomplished by using either total or partial dynamic reconfiguration. ...
doi:10.12720/ijeee.3.3.234-239
fatcat:f4zesfcrgvbcpbrjx6thpvpere
A review of high-level synthesis for dynamically reconfigurable FPGAs
2000
Microprocessors and microsystems
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In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. ...
Finally, techniques that have been developed in the past few years for the high-level synthesis of dynamically reconfigurable systems are presented. ᭧ ...
Another system which is concerned with an integrated synthesis and partitioning strategy for adaptive and reconfigurable computer systems is the SPARCS system, which is an integrated design environment ...
doi:10.1016/s0141-9331(00)00074-0
fatcat:j2udiqvfvja3xieopntaquluce
HW/SW codesign techniques for dynamically reconfigurable architectures
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Her research interests include computer-aided design tools for very large scale integration (VLSI), reconfigurable architectures, performance prediction, analysis of message-passing applications, and GRID ...
Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. ...
ACKNOWLEDGMENT The authors acknowledge the Department of Research and Development of Hewlett-Packard Inkjet Commercial Division, Barcelona, Spain, for its support in the preparation of his Ph.D. dissertation ...
doi:10.1109/tvlsi.2002.801575
fatcat:3ojhhmr27fgxzcuvvj2xwbmyf4
On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures
2003
IEEE transactions on computers
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Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. ...
This paper proposes a novel algorithm for automated datapath design, from behavioral input descriptions (represented by a dataflow graph), which simultaneously performs temporal partitioning and sharing ...
Figure 1a) shows a design flow which integrates temporal partitioning prior to the highlevel synthesis tasks [8] . ...
doi:10.1109/tc.2003.1234532
fatcat:wwp7mw66qvbhlksy2fmkx3jyza
Ecoscale: Reconfigurable Computing And Runtime System For Future Exascale Systems
2016
Zenodo
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The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming ...
ECOSCALE tackles these challenges by proposing a scalable programming environment and architecture, aiming to substantially reduce energy consumption as well as data traffic and latency. ...
This research project is supported by the European Commission under the H2020 Programme and the ECOSCALE project (grant agreement 671632). ...
doi:10.5281/zenodo.34893
fatcat:ocwfndo4vjei3hqucmndj22xu4
Power-performance trade-offs for reconfigurable computing
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
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We show that an efficient hardware-software partitioning algorithm is required when targeting low-power. ...
We propose a design methodology that adapts the architecture and used algorithms to the application requirements. ...
RELATED WORK In [4] an integrated algorithm for HW/SW partitioning and scheduling, temporal partitioning and context scheduling is presented. ...
doi:10.1145/1016720.1016751
dblp:conf/codes/NogueraB04
fatcat:kmujsufot5gzxnejo72so72t4y
Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)
2007
it - Information Technology
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This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level ...
Moreover, the implementation of selected solutions poses an additional challenge and also requires a cycle-level simulation. ...
For this purpose, we propose the integration of temporal partitioning algorithms into the design space exploration. ...
doi:10.1524/itit.2007.49.3.149
fatcat:gaabsiltkzhq3h54wcou2qw6he
Runtime Adaptive Extensible Embedded Processors — A Survey
[chapter]
2009
Lecture Notes in Computer Science
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However, due to the limited area available for implementation of custom instructions in the datapath of the processor core, we may not be able to exploit all custom instruction enhancements of an application ...
In this article, we provide a detailed survey of the contemporary architectures that offer such dynamic instruction-set support and discuss compiler and/or runtime techniques to exploit such architectures ...
Acknowledgements This work is partially supported by NUS research project R-252-000-292-112. ...
doi:10.1007/978-3-642-03138-0_23
fatcat:dmhl3mmoxrhfhhcanrryjt5tum
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures
2007
IEICE transactions on information and systems
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Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. ...
By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. ...
Related Work Ganesan and Vemuri [6] presented a novel partitioning methodology that temporally partitions a design for a partially reconfigurable processor and improves design latency by minimizing reconfiguration ...
doi:10.1093/ietisy/e90-d.12.1977
fatcat:l7zkqoe42zd4ncdxra32iu6dhq
Smart technologies for effective reconfiguration: The FASTER approach
2012
7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
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at run time, the capabilities of partial dynamic reconfiguration. ...
The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification ...
Based on these objectives, a new model for addressing reconfiguration in dynamically reconfigurable FPGAs and new graph-theoretic algorithms for the temporal and spatial partitioning of a specification ...
doi:10.1109/recosoc.2012.6322881
dblp:conf/recosoc/SantambrogioPPPGSDBTLBCDS12
fatcat:eplvqvzqmfdirggcfr4qb53neq
A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs
2008
EURASIP Journal on Embedded Systems
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Higher level of abstraction, design space exploration, hardware/software partitioning, codesign, rapid prototyping, virtual component design and integration for heterogeneous architectures; all these topics ...
Application-specific integrated circuits (ASICs) are a partial solution for these needs. ...
doi:10.1155/2008/793919
fatcat:con7yeic5jftrhyp54vdvneoyi
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