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A hierarchical analysis approach for high performance computing and communication applications
Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences. 1999. HICSS-32. Abstracts and CD-ROM of Full Papers
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The proliferation of high performance computers and high-speed networks has made parallel and distributed computing feasible and cost-effective on High Performance Computing and Communication Systems ( ...
This paper presents a three-level hierarchical modeling approach for analyzing the end-to-end performance of an application running on an HPCC system. ...
Conclusion In this paper, we presented a three-level hierarchical analysis approach to analyze the performance of a High Performance Computing and Communication system and its applications. ...
doi:10.1109/hicss.1999.772833
dblp:conf/hicss/HaririVZXG99
fatcat:p7tve4luibd75fr3q7dxi5ptgi
Hierarchical Dataflow Model for efficient programming of clustered manycore processors
2017
2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
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Dataflow Models of Computation (MoCs) are increasingly used for developing parallel applications as their high-level of abstraction eases the automation of mapping, task scheduling and memory allocation ...
This paper introduces a technique for deploying hierarchical dataflow graphs efficiently onto MPSoC. ...
Clustered architectures [1] are also a promising step towards high performance on-chip computing. ...
doi:10.1109/asap.2017.7995270
dblp:conf/asap/HascoetDND17
fatcat:zrl6ffctonhrzixhzhh35nbzdy
A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems
2008
2008 20th International Symposium on Computer Architecture and High Performance Computing
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Using our analysis and projection results, we obtain insight into the performance characteristics of the application on a quad-core system and also identify optimal mapping on a Teraflops-scale platform ...
Traditional performance optimization, tuning and modeling techniques that rely on uniform representation of computation and communication requirements are only partially useful due to the complexity of ...
The authors would like to thank Xingfu Wu (TAMU), Heike Jagode (UTK-ORNL), Jeff Candy (General Atomi), and Mark Fahey (ORNL) for reviews of this work. ...
doi:10.1109/sbac-pad.2008.27
dblp:conf/sbac-pad/LivelyTAV08
fatcat:sjwcphf2kvaldm2s3uchx6ayse
Communication-Oriented Design Space Exploration for Reconfigurable Architectures
2007
EURASIP Journal on Embedded Systems
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It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. ...
The aim is to increase the synergy between the application and the architecture in order to get the best performance. ...
We propose in this paper an original approach based on a high-level representation of the application and on a hierarchical functional model for the architecture. ...
doi:10.1155/2007/23496
fatcat:r3byspfuq5hdzlpocaqbykyrau
Communication-Oriented Design Space Exploration for Reconfigurable Architectures
2007
EURASIP Journal on Embedded Systems
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It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. ...
The aim is to increase the synergy between the application and the architecture in order to get the best performance. ...
We propose in this paper an original approach based on a high-level representation of the application and on a hierarchical functional model for the architecture. ...
doi:10.1186/1687-3963-2007-023496
fatcat:y6weazz5ofcxtdvwtf2nd77tca
Adapting wave-front algorithms to efficiently utilize systems with deep communication hierarchies
2011
Parallel Computing
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A performance model is used to quantify this trade-off and show that, for a range in the performance-space consisting of core computation performance, inter-domain communication performance and blocking ...
The approach is generally applicable to large-scale multi-core and accelerated systems where a differential in communication performance exists. ...
However the communication performances to other parts of a system degrade significantly and can pose a bottleneck for many applications. ...
doi:10.1016/j.parco.2011.02.008
fatcat:z6x2jsgy7nc4xi7acduyxvplye
Topology-Aware Mapping Techniques for Heterogeneous HPC Systems: A Systematic Survey
2018
International Journal of Advanced Computer Science and Applications
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As a consequence, the communication costs and the data movement are increasing. ...
It will also decrease the communication cost of the processes by matching the application virtual topology (exploited by the system for assigning the processes to the physical processor) to the target ...
the increasing hierarchical, heterogeneous and complex nature of the current and future high-performance computing (HPC) platforms. ...
doi:10.14569/ijacsa.2018.091045
fatcat:taeescyyjjej7pbqutm4kulagy
Modular Visualization of Distributed Systems
2011
CLEI Electronic Journal
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We havedeveloped OverView, a tool for online/offline distributed systems visualization, that enables modular layout mechanisms, so that different distributed system high-level programming abstractions ...
In this paper, we develop a force-directed layout strategy that connects entities according to their communication patterns in order to directly exhibit the application communication topologies. ...
Consider a scientist who would like to observe the interactions between computers while they run a high performance parallel simulation. ...
doi:10.19153/cleiej.14.1.7
fatcat:3kvvbo4rpbeuhomucjdqsyii54
Shared resources high-level modeling in embedded systems using virtual nodes
2009
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference
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The overall approach is based on using a specific UML modeling profile and a SystemC-based simulator to execute models and analyze their performance. ...
in the early design stages, by means of modeling the design at a high level of abstraction. ...
We use, as well, the hierarchical composition of virtual nodes for computation, communication and storage resource sharing. ...
doi:10.1109/newcas.2009.5290506
fatcat:7afn4pjfkra3temhp7dru2idfi
Computer configurations
1987
Proceedings of the IEEE
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The paper shows how configurations have evolved and in today's systems there is much commonality in approach. ...
Computer system architectures have changed significantly over the years because of changing requirements from utilities and changes in the available hardware and software technology. ...
Thus the modern advanced applications have created a need for high-precision storage and fast manipulation of high-resolution floating-point numbers. ...
doi:10.1109/proc.1987.13933
fatcat:7473vadnjvaeff3b4ircyx57t4
Design of a multimedia processor based on metrics computation
2005
Advances in Engineering Software
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The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. ...
This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. ...
CP is computed for each hierarchical level with a data and control dependency analysis. Our analysis method is not exclusively statistical contrary to [5] metrics. ...
doi:10.1016/j.advengsoft.2005.01.010
fatcat:lo2d45p4mbasbjut5745cifn74
A Batch Task Migration Approach for Decentralized Global Rescheduling
2018
2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
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Effectively mapping tasks of High Performance Computing (HPC) applications on parallel systems is crucial to assure substantial performance gains. ...
As platforms and applications grow, load imbalance becomes a priority issue. ...
ACKNOWLEDGEMENTS The authors acknowledge the National Laboratory for Scientific Computing (LNCC/MCTI, Brazil) for providing HPC resources of the SDumont supercomputer, which have contributed to the research ...
doi:10.1109/cahpc.2018.8645953
dblp:conf/sbac-pad/FreitasSCP18
fatcat:yeozzxgebrdalh5pvsos37qiai
Scalable data race detection for partitioned global address space programs
2013
SIGPLAN notices
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Bug finding for distributed memory programming models is made scalable by using a distributed analysis, but the current approaches illustrated by DAMPI and UPC-Thrille track only the calls into communication ...
Introduction Attaining good performance and efficacy on contemporary and future large scale High Performance Computing systems requires using hybrid programming models: OpenMP+MPI, UPC+MPI, Intel TBB + ...
doi:10.1145/2517327.2442557
fatcat:brwq6os2vvghhoy6nkgkim7afq
Scalable data race detection for partitioned global address space programs
2013
Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '13
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Bug finding for distributed memory programming models is made scalable by using a distributed analysis, but the current approaches illustrated by DAMPI and UPC-Thrille track only the calls into communication ...
Introduction Attaining good performance and efficacy on contemporary and future large scale High Performance Computing systems requires using hybrid programming models: OpenMP+MPI, UPC+MPI, Intel TBB + ...
doi:10.1145/2442516.2442557
dblp:conf/ppopp/ParkSI13
fatcat:dhpqiohp5vhppkmkvz73ttkbuu
A Comparative Study and Analysis of Data Aggregation Techniques in WSN
2015
Indian Journal of Science and Technology
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Application: The survey will help to identify the data aggregation algorithm suitable for a specific application. ...
, communication pattern, query based support, energy usage and application type. ...
This approach is efficiently used for event based applications and it follows a Randomized Waiting (RW) approach. ...
doi:10.17485/ijst/2015/v8i26/81713
fatcat:vs4at4teqzdbtkjua3pb3c4gii
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