UC Berkeley Architecture Research
- 850 followers
- Berkeley, CA
- http://bar.eecs.berkeley.edu
- info@riscv.org
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- chia Public
An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
ucb-bar/chia’s past year of commit activity - zephyr-chipyard-sw Public
ucb-bar/zephyr-chipyard-sw’s past year of commit activity - chia_benchmarks Public
ucb-bar/chia_benchmarks’s past year of commit activity - cacti Public Forked from HewlettPackard/cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
ucb-bar/cacti’s past year of commit activity - chipyard Public
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
ucb-bar/chipyard’s past year of commit activity - rocket-chip-inclusive-cache Public Forked from chipsalliance/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
ucb-bar/rocket-chip-inclusive-cache’s past year of commit activity
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