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abhichandra586/README.md

Hi, I'm Abhi Chandra 👋

3rd year B.Tech ECE student at Vignan's Institute of Information Technology, Visakhapatnam. Building a career in VLSI design — from fundamentals to silicon.

About Me

  • 🎓 B.Tech ECE — 3rd Year | CGPA: 9.68 ( 3 semesters cumulative )
  • 🔧 Specialising in RTL design, digital verification, and FPGA implementation
  • 🛰️ Built a CubeSat telemetry system (ESP32 + LoRa + multiple sensors)
  • 🤖 Built AuraGlove — a gesture recognition glove
  • 📖 Preparing for GATE ECE 2027 in parallel

VLSI Portfolio — 8 Repositories

A structured, self-directed build from logic gates to a complete 16-bit pipelined RISC processor on FPGA.

# Repository Status Contents
01 basic-logic-gates ✅ Complete AND, OR, NOT, NAND, NOR, XOR, XNOR
02 combinational-circuits ✅ Complete Adders, MUX, Decoder, Encoder, Comparator, 16-bit ALU
03 sequential-circuits ✅ Complete Flip-Flops, Registers, Counters, Shift Registers, SRAM
04 finite-state-machines 🔨 In progress Moore FSM, Mealy FSM, UART, SPI, Debounce
05 05-alu-16bit ⏳ Upcoming SystemVerilog ALU + Assertions + Synthesis
06 06-processor-components ⏳ Upcoming PC, Control Unit, Register File, Hazard Unit
07 07-risc16-pipelined-processor ⏳ Upcoming Complete 5-stage pipelined RISC processor
08 08-protocols-and-interfaces ⏳ Upcoming UART, SPI, AXI4-Lite in SystemVerilog

Other Projects

🛰️ CubeSat Telemetry System

Real-time environmental and inertial data acquisition and wireless transmission system simulating a CubeSat data downlink.

  • Hardware: ESP32, INA219, BMP280, DHT11, MPU6050, SX1278 LoRa
  • Communication: LoRa at 433 MHz — 2km+ range
  • Skills: Embedded C, SPI, I2C, PCB design, sensor integration

🤖 AuraGlove — Gesture Recognition Glove

Wearable glove that recognises hand gestures and maps them to commands.

  • Hardware: Flex sensors, IMU, microcontroller
  • Skills: Signal processing, embedded firmware, hardware prototyping

Tech Stack

Hardware Description Verilog HDL · SystemVerilog · RTL Design

Simulation & Synthesis Icarus Verilog · GTKWave · Yosys · Vivado

Embedded Systems ESP32 · Arduino · C/C++ · SPI · I2C · UART · LoRa

Tools Git · GitHub · VS Code · Linux

Currently

  • 🔨 Building Repo 4 — Finite State Machines (Moore, Mealy, UART, SPI)
  • 📖 GATE ECE 2027 preparation running in parallel
  • 🎯 Target: Complete 16-bit pipelined RISC processor by October 2026

Connect

Building from AND gate to a complete 16-bit pipelined RISC processor — one module at a time.

Pinned Loading

  1. 01-basic-logic-gates 01-basic-logic-gates Public

    Basic Logic Gates in Verilog — AND, OR, NOT, NAND, NOR, XOR, XNOR | Step 1 of 8 toward a 16-bit pipelined RISC processor

    Verilog 3

  2. 02-combinational-circuits 02-combinational-circuits Public

    Combinational circuits in Verilog - Adders, Subtractor, MUX, Decoder, Encoder, Comparator and 16-bit ALU. Step 2 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.

    Verilog 3

  3. 03-sequential-circuits 03-sequential-circuits Public

    Sequential circuits in Verilog — Flip-Flops, Registers, Counters, Shift Registers and Synchronous SRAM. Step 3 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.

    Verilog 1

  4. 04-finite-state-machines 04-finite-state-machines Public

    Finite State Machines in Verilog — Moore FSM, Mealy FSM, Traffic Light Controller, Sequence Detector (1011), UART Transmitter, UART Receiver, SPI Master, Debounce Circuit | Step 4 of 8 toward a 16-…

    Verilog 1