Fixed-complexity sphere decoder (FSD) is one of the most promising techniques for the implementation of multiple-input multiple-output (MIMO) detection, with relevant advantages in terms of constant throughput and high flexibility of parallel architecture. The reported works on FSD are mainly based on software level simulations and a few details have been provided on hardware implementation. In this paper, we present the study based on a four-nodes-per-cycle parallel FSD architecture with

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... l examples of VLSI implementation in 4 × 4 systems with both 16-QAM and 64-QAM modulation and both real and complex signal models. Implementation aspects and details of the architecture are analyzed in order to provide a variety of performance-complexity trade-offs. We also provide a parallel implementation of log-likelihood-ratio (LLR) generator with optimized algorithm to enhance the proposed FSD architecture to be a soft-input soft-output (SISO) MIMO detector. To our best knowledge, this is the first complete VLSI implementation of an FSD based SISO MIMO detector. The implementation results show that the proposed SISO FSD architecture is highly efficient and flexible, making it very suitable for real applications. Multiple-input multiple-output (MIMO) system is one of the most important elements of novelty in next generation wireless communications, and provides increased data throughput and link range without additional bandwidth and transmit power [1] . It has already been included in multiple wireless communications standards, such as the IEEE 802.16e WiMax and the 3rd generation partnership project (3GPP) long term evolution ( LTE) [2]. A large variety of MIMO detection techniques have been proposed, including the family of sphere decoders (SD). The originally proposed sphere decoder performs depth-first tree traversal by employing Schnorr-Euchner enumeration (SESD) [3]. This technique achieves maximum-likelihood (ML) performance and its hardware implementation has been extensively explored in both hard and soft output versions [4] [5] [6]. Unfortunately the SESD offers an intrinsically variable throughput, which tends to decrease significantly at low signal-to-noise ratio (SNR) [4] [5]. Another disadvantage of the SESD is the sequential tree search order, which makes it difficult to employ parallel architectures to improve the throughput. Different forms of pipelining have been proposed to avoid this SD drawback [7] [8]. Some sub-optimal algorithms, such as the K-best algorithm and the fixed-complexity sphere decoder (FSD), are proposed to obtain constant throughput and reduce hardware complexity, with an acceptable degree of performance loss [9] [10]. Receivers with concatenated MIMO detection and channel decoding have been recently proposed using powerful error correcting codes, such as Turbo and low-density paritycheck (LDPC) codes in order to achieve near-capacity performance [11]. Soft information could be obtained by extending the existing hard-output sphere decoders, which could be SESD, K-best SD or FSD, into a list sphere decoder (LSD), which generates a list of candidates instead of the only ML solution. Then the log-likelihood-ratios (LLR) are evaluated based on the list and the a-priori information. Finally the LLRs are forwarded to the channel decoder [9] [12] [13]. Although the soft-output SESD achieves optimal performance, it still suffers from variable throughput [14] , and the performance drops dramatically when the number of visited nodes is bounded in order to limit the complexity and the latency in hardware POS_LIST and MIN_LIST in Fig. 5 , which contain Q k i for the candidates with x i,k = +1 or x i,k = −1 respectively. If Q k i is moved into one of the two lists, it is compared with the current value in the corresponding register, which is set to be the minimum possible value LLR_MIN at the beginning. When Q k i is greater than the current registered value, The