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CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector
2016
Circuits and Systems
This paper describes the design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic Multiple-Input-Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance
doi:10.4236/cs.2016.78152
fatcat:b4ixu2ly3beg5eh4qmu6jxl2gy