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Run-time verification using the VHDL-AMS simulation environment
2007
2007 IEEE Northeast Workshop on Circuits and Systems
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In this paper, we propose a run-time verification approach for VHDL-AMS designs. The essence of this approach is the construction of timed automata from the given specification. ...
For illustration purposes, we applied the approach using VHDL-AMS simulation environment for the verification of a PLL design. ...
The main challenge in monitoring AMS designs is the development of adequate monitors able to express the properties. In this paper, we propose a run-time verification approach for VHDL-AMS designs. ...
doi:10.1109/newcas.2007.4488030
fatcat:iwfj3zfmujat5kkvunygh3ixu4
System level design and verification using a synchronous language
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
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Case studies include examples of design space exploration by synthesizing equivalent hardware or software from the same Esterel description, with formal verification of safety properties such as bus protocol ...
Esterel models have proved to be useful for rapid design space exploration and verification at system level, without resorting to detailed implementation and slow bit-level event-based simulation. ...
Such a flow has many desirable properties, including the ability to keep a single specification for hardware and software while formally guaranteeing the same behavioral properties of the design. ...
doi:10.1109/iccad.2003.159720
fatcat:7sidxprs4zgfffv7h5e6rdix74
Design and Verification of CoreConnectTM IP Using Esterel
[chapter]
2003
Lecture Notes in Computer Science
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We describe experiments to design and build working hardware based around IBM's CoreConnectTM Intellectual Property (IP) bus. ...
This paper explores the practicality of describing and verifying both the hardware and software components of System-on-Chip (SOC) architectures using Esterel. ...
"Virtex-II" is a trademark of Xilinx Inc. "CoreConnect" is a trademark of IBM. We would like to thank the staff at Esterel Technologies for their generous assistance during this project. ...
doi:10.1007/978-3-540-39724-3_26
fatcat:yxiobw3jrzdn7kw35o2bzdg7j4
Control Interpreted Petri Nets - Model Checking and Synthesis
[chapter]
2012
Petri Nets - Manufacturing and Computer Science
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(but are not limited to) model checking of other forms of logic controllers specification and mechanisms for behavioural properties specification. ...
Schema of proposed system for designing of logic controllers is presented in Figure 2 . specification is prepared by means of Control Interpreted Petri Nets [8] . ...
doi:10.5772/47797
fatcat:ggtegcoakze5po56mgakchhrgm
Checking properties of PLL designs using run-time verification
2007
2007 Internatonal Conference on Microelectronics
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In this paper, we propose a run-time verification approach for PLL designs. ...
Due to challenges associated with its verification process, analog and mixed signal designs like PLLs require a considerable portion of the total design time. ...
In [5] , a run-time verification approach for VHDL-AMS designs is proposed, in which the properties of interest are monitored by timed automata. ...
doi:10.1109/icm.2007.4497676
fatcat:pvlp66acpzcyzeg7muaik7e7ty
Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers
2001
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01
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The verification cycle time reduction and the salient features of an automated methodology that was developed specifically for our DSP core are described. ...
Formal verification plays an important role in the verification of complex processors. ...
RTL-to-RTL verification of C3 sub designs versus C1 sub designs 2. RTL (VHDL)-to-Netlist(MCL) verification for the blocks coded in MCL. 3. ...
doi:10.1145/370155.370316
dblp:conf/aspdac/ChandarV01
fatcat:dbx3mvifrnfyddcnzpnxa6qp64
System synthesis utilizing a layered functional model
1999
Proceedings of the seventh international workshop on Hardware/software codesign - CODES '99
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Thus, without compromising the formal properties of the abstract system model we provide an efficient synthesis method. ...
Because of this restriction cost measures can be developed to control and predict performance and cost of an implementation, as elaborated in [12] . ...
control constructs to facilitate also the modelling of complex control flow and is executable to allow the simulation of the system model. ...
doi:10.1145/301177.301510
dblp:conf/codes/SanderJ99
fatcat:hxckizu4ebhpvljcsm3yvixevm
High Level Synthesis Using Operation Properties
[chapter]
2010
Lecture Notes in Electrical Engineering
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Furthermore, operation properties are well suited for specifications of consecutive operations of finite length. ...
A major advantage of using operation properties as a design method is the existence of commercial tools to check the completeness and consistency of the property set. ...
SYNTHESIS ALGORITHM In this section we first propose an algorithm to synthesize the control flow of the design. ...
doi:10.1007/978-90-481-9304-2_11
fatcat:gxux5eeodzbtxof2jqnarumn4i
From VHDL to efficient and first-time-right designs: a formal approach
1996
ACM Transactions on Design Automation of Electronic Systems
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To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent ...
in VHDL. ...
Algorithms written in Pascal or Behavioral VHDL used for specification are translated into an Extended Timed Petri Net representation in which data and control flow are separated. ...
doi:10.1145/233539.233541
fatcat:yq72f3twtzeyxgwdmm7kbzkcyq
Semi‐formal specifications and formal verification improving the digital design: some statistics
2009
Journal of Applied Research and Technology
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The major change is the use of a semiformal specification for the code implementation, the use of a verification tool and the establishment of properties for the formal verification of Finite State Machines ...
Finally, a set of properties for the verification of this module were established and proved using a model checking tool. ...
Likewise, they would like to acknowledge Safelogic for allowing them to use the safelogic verifier for the formal verification process of their code ...
doi:10.22201/icat.16656423.2009.7.01.498
fatcat:ze7uchhoqnhdval6xolsqdqc3a
From Assertion-Based Verification to Assertion-Based Synthesis
[chapter]
2011
IFIP Advances in Information and Communication Technology
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We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. ...
We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. It uses concepts from the Assertion-Based Verification. ...
Fig. 2 . 2 Trace with several activations of Start
Fig. 3 . 3 Design flow including the functional verification of a hand-coded RTL design
Fig. 4 . 4 Design flow with automatic synthesis of the RTL ...
doi:10.1007/978-3-642-23120-9_6
fatcat:qltusvyusnh7hcpt2tzldxca5a
Design-flow and synthesis for ASICs
1995
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95
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phases of the design flow. ...
The growing complexity of devices to be designed and manufactured, and the need to reduce the time-to-market, stress the importance of sound design methodologies. ...
For this reason these two parameters must be kept under control even at the highest levels of specification and partitioning. ...
doi:10.1145/217474.217544
dblp:conf/dac/BombanaCCHMZ95
fatcat:iovpvob7d5hvpczrikhgaatmna
Design-Flow and Synthesis for ASICs: A Case Study
1995
Proceedings - Design Automation Conference
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phases of the design flow. ...
The growing complexity of devices to be designed and manufactured, and the need to reduce the time-to-market, stress the importance of sound design methodologies. ...
For this reason these two parameters must be kept under control even at the highest levels of specification and partitioning. ...
doi:10.1109/dac.1995.249962
fatcat:5ulddl4rrraqpgz5wleeb5o6du
Fast prototyping
1999
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99
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This flow, called Fast Prototyping, enables concurrent hardware and software development, early verification and productive re-use of intellectual property. ...
This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based System-On-Chip designs. ...
FAST PROTOTYPING This methodology defines a flow for fast SOCs design. ...
doi:10.1145/309847.309971
dblp:conf/dac/ClementHLRCP99
fatcat:wkdwm6bstjfhfcksh66yz2hshu
Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do
[chapter]
2009
Lecture Notes in Computer Science
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to prove the design is correct. ...
However, clear distinctions exist in the design tools. ...
Findings contained herein are not necessarily those of the FAA. ...
doi:10.1007/978-3-642-04468-7_17
fatcat:kecmx2fqbzdcroisstidgpcpl4
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