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A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier
2014
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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The prototype ADC fabricated in 65 nm CMOS demonstrates an ENOB of 7.88 bits up to 30 MS/s with an input close to the Nyquist frequency at 0.6 V. ...
This paper presents a 0.5-to-1 V, 9-bit, 15-to-90 MS/s digitally interpolated pipelined-SAR ADC. ...
Fig. 8 . 8 FFT of the measured results with (a) 1 MHz and (b) 14 MHz input sampled at 30 MS/s (4096 data points).
Fig. 9 .Fig. 10 . 910 Chip photo of the prototype ADC. ...
doi:10.1109/asscc.2014.7008866
dblp:conf/asscc/LinXMM14
fatcat:jrbv3uwee5ebtbwwiay3wm2kee
A fast, ultra-low and frequency-scalable power consumption, 10-bit SAR ADC for particle physics detectors
2015
Journal of Instrumentation
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A : The design and measurements results of a fast 10-bit SAR ADC with ultra-low and scalable with frequency power consumption, developed for readout systems for detectors at future particle physics colliders ...
and quantify the ADC performance. ...
Acknowledgments This work was supported by Polish National Science Centre (NCN), grant reference number DEC-2012/07/B/ST7/01456. ...
doi:10.1088/1748-0221/10/11/p11012
fatcat:4jrztnsg2nc2tjylkf6bmqm4um