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Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors
2015
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Index Terms-Dynamic voltage and frequency scaling (DVFS), multicore processors, switched capacitor (SC). ...
A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency. ...
Per-Core DVFS Model Given a target speed for the processor core, the complete model calculates the energy per cycle for a system that contains one processor core, the reconfigurable dc-dc converter, and ...
doi:10.1109/tvlsi.2014.2316919
fatcat:wqu5c7b5nzgvbggv4ejgalqt3q
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System
2021
ACM Transactions on Architecture and Code Optimization (TACO)
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The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). ...
We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads. ...
ACKNOWLEDGEMENTS We are grateful to the reviewers for their constructive feedback. ...
doi:10.1145/3468145
fatcat:5lzgnkcsdvgmhkvrwphteflnne
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture
2012
IEEE International Symposium on High-Performance Comp Architecture
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Experimental results show that the hybrid scheme achieves performance-energy efficiency close to per-core DVFS, without imposing much design cost. ...
The widening gap between the fast-increasing transistor budget but slow-growing power delivery and system cooling capability calls for novel architectural solutions to boost energy efficiency. ...
[37] proposed a scalable power control al-gorithm for per-core DVFS tuning for a mesh-like manycore processors. ...
doi:10.1109/hpca.2012.6169034
dblp:conf/hpca/YanLHLGL12
fatcat:zacug5pgh5agtkmodvqayxecim
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
[article]
2021
arXiv
pre-print
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In addition, DarkGates fulfills the requirements of the ENERGY STAR and the Intel Ready Mode energy efficiency benchmarks of desktop systems. ...
DarkGates maintains the performance of 3DMark workloads for desktop systems with TDP greater than 45W while for a 35W-TDP (the lowest TDP) desktop it experiences only a 2% degradation. ...
constrained Multicore Processors using DVFS and Per-core Power-gating,” in [56] P. ...
arXiv:2112.11587v1
fatcat:snli37hdubdjfbt553znhtw33q
Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors
2016
ACM Transactions on Design Automation of Electronic Systems
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In order to be scalable to manycore systems, the hierarchical control scheme is designed with two levels. ...
The new method employs model predictive control (MPC) with task migration and a DVFS scheme to ensure smooth control behavior and negligible computing performance sacrifice. ...
This could be a serious problem in many-core systems, especially for per-core DVFS. ...
doi:10.1145/2891409
fatcat:j5b7u3b3avhh5dgmdwyowyy62q
System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs
2014
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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He was an Intern with Indrion Technologies, Bangalore, India, in 2008, where he worked on developing energy-efficient instruction set extensions for a sensor control network processor. ...
Further, the scheme is applied to a stack partitioned into voltage islands, where it is shown to match the conventional per-core DVFS schemes in its performance. ...
Finally, our scheme when applied to a voltage island partitioned 3-D stack, was found to perform at par with per-core 2-D DVFS, with a 60% lower area overhead in terms of level shifters and voltage converters ...
doi:10.1109/tvlsi.2013.2273003
fatcat:mlpcivb3pbh67g6ohulcmpv3ze
D5.2: Best Practices for HPC Procurement and Infrastructure
2013
Zenodo
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Specific areas of interest are analysed in depth in terms of the market they belong to and the general HPC landscape, with a particular emphasis on the European point of view. ...
Task 2 – Best practices for designing and operating power efficient HPC centre infrastructures – has continued the production of white papers which explore specific topics related to HPC data c [...] ...
This system is announced for 2014 and it will use one 4-core processor per node with a performance of 256 GFlop/s and 256 GB/s memory bandwidth (1 byte per flop ratio). ...
doi:10.5281/zenodo.6572412
fatcat:2bqftmr5zzb7na6pnlrlxxuqnu
On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions
2019
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)
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The expectation for the probability of 1 at some position in the response, the Bit-Alias, is a state-of-the-art metric in this regard. ...
Physical Unclonable Functions (PUFs) are modern solutions for cheap and secure key storage. ...
While bipolar transistors are utilized for reference and temperature dependent voltage generation in a switched-capacitor band-gap core, the overall temperature sensor is formed by a combination of the ...
doi:10.1109/newcas44328.2019.8961298
dblp:conf/newcas/WildeP19
fatcat:wv67uzuqlvcmhma3nahzdrr2ta
A Survey of Resource Management for Processing-in-Memory and Near-Memory Processing Architectures
[article]
2020
arXiv
pre-print
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In this article, we survey the major trends in managing PIM and NMP-based DCC systems and provide a review of the landscape of resource management techniques employed by system designers for such systems ...
Therefore, designing intelligent resource management techniques for computation offloading is vital for leveraging the potential offered by this new paradigm. ...
Energy Efficiency DCC architectures have demonstrated tremendous potential for energy efficiency due to a reduction in expensive off-chip data movement, the use of energy-efficient PEs, or by using NVM ...
arXiv:2009.09603v1
fatcat:aylcbzdsrrdbzgifdqxqs2wcaq
Eurolab-4-HPC Long-Term Vision on High-Performance Computing
[article]
2018
arXiv
pre-print
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Radical changes in computing are foreseen for the next decade. ...
, software, and applications in High-Performance Computing (HPC). ...
Certain techniques for energy efficiency (near threshold, DVFS, energyefficient interconnects) increase timing variability among the processes in an HPC application. ...
arXiv:1807.04521v1
fatcat:5neetrgubjhnvcajcktpkohrzq
Data Gathering and Resource Measuring
[chapter]
2022
Fundamentals
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This book starts with chapters ordered in analogy to the data analysis workflow before it investigates particular resources. Data is the raw material for all machine learning applications. ...
This chapter discusses approaches and tools to handle data collecting in embedded systems. First, a framework for collection of complex operating system data is presented with kCQL. ...
We also measure both quantities for SystemTap and PiCO QL for comparison. Our evaluation platform is a desktop computer with an Intel Core i5-3570 processor and Ubuntu Server 14.04. ...
doi:10.1515/9783110785944-002
fatcat:tlyqygrb5jgs3bztzh5imssv2q
Design for Reliability and Low Power in Emerging Technologies
2021
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Die fortlaufende Verkleinerung von Transistor-Strukturgrößen ist einer der wichtigsten Antreiber für das Wachstum in der Halbleitertechnologiebranche. ...
Dazu zählen, unter anderem, Alterungseffekte in Transistoren sowie übermäßige Hitzeentwicklung, nicht zuletzt durch stärkeres Auftreten von Selbsterhitzungseffekten innerhalb der Transistoren. ...
Power efficiency measured in performance-per-watt is now the metric for evaluation of manycore designs. ...
doi:10.5445/ir/1000137950
fatcat:adcjcweifreytfrfmlt6hbd3vy
RA-LPEL: A Resource-Aware Light-Weight Parallel Execution Layer for Reactive Stream Processing Networks on The SCC Many-core Tiled Architecture
[article]
2016
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Further, we have developed a Dynamic Voltage and Frequency Scaling (DVFS) technique for RSP deployed on many-core architectures. ...
In contrast to many other approaches, our DVFS technique does not require the capability of controlling the power settings of individual computing elements, thus making it applicable for modern many-core ...
The experimental results confirm that the proposed DVFS technique can effectively improve the energy efficiency, i.e. increase the performance per watt, for RSPs. ...
doi:10.18745/th.17225
fatcat:lunf25ikfngmlijsjpgycp2mem
Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors
2015
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However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. ...
In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. ...
For example, we observed a 12 % higher switching activity at the inputs of the instruction buffer (SRAM-based) corresponding to the opcode bits for the aging-aware ISE (see Section 6.2.4). ...
doi:10.5445/ir/1000045647
fatcat:cdfhlaerzfc37il7py4uydt3cy