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A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems
2016
IEEE Transactions on Parallel and Distributed Systems
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In this paper, we present a survey of software techniques that have been proposed to exploit the advantages and mitigate the disadvantages of NVMs when used for designing memory systems, and, in particular ...
Given that NVMs are growing in popularity, we believe that this survey will motivate further research in the field of software technology for NVMs. ...
Since the erroneous data in write-through SSD caches can be recovered by accessing the HDD, one of their technique converts the uncorrectable errors into cache misses that bring in valid data from HDD. ...
doi:10.1109/tpds.2015.2442980
fatcat:ewuxh7wj3jarzkykdw37o6aufy
Phase Change and Magnetic Memories for Solid-State Drive Applications
2017
Proceedings of the IEEE
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DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. ...
in terms of latency and reliability. ...
the depends on the amount of hot data that are stored in memory along with other cached data. ...
doi:10.1109/jproc.2017.2710217
fatcat:fof3pr2ixjfqdd3f226s4qqh7e
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory
[article]
2018
arXiv
pre-print
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We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes ...
The key idea of ROR is to periodically learn a tight upper bound of the optimal read reference voltage, and from there approach the optimal read reference voltage. ...
This work is partially supported by the Intel Science and Technology Center, CMU Data Storage Systems Center, and NSF grants 1212962 and 1320531. ...
arXiv:1805.02819v1
fatcat:43t2wathnredppbbb6v3j23jxu
Read Disturb Errors in MLC NAND Flash Memory
[article]
2018
arXiv
pre-print
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For the first time in open literature, this work experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. ...
The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. ...
This work is partially supported by the Intel Science and Technology Center, the CMU Data Storage Systems Center, and NSF grants 0953246, 1065112, 1212962, and 1320531. ...
arXiv:1805.03283v1
fatcat:swhmawggyrbdfi25gx6jtditg4
Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives
[article]
2017
arXiv
pre-print
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cell sensing, (3) error correction using state-of-the-art algorithms and methods, and (4) data recovery when error correction fails. ...
In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. ...
A version of the paper is published as an invited article in Proceedings of the IEEE [11] . This version is almost identical to [11] . ...
arXiv:1706.08642v3
fatcat:ozzc62npvzewhgkb54ebvnh5ta
Amnesic cache management for non-volatile memory
2015
2015 31st Symposium on Mass Storage Systems and Technologies (MSST)
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In this paper, we take a different approach that makes use of the limited retention capability to our advantage. ...
This retention relaxation can enhance the overall cache performance in terms of latency and energy since the data retention capability is proportional to the write latency. ...
Again, the same tradeoff is also observed in STT-RAM where high thermal stability makes the cell more tolerable to random bit-flips, while making it more difficult to write [5] . ...
doi:10.1109/msst.2015.7208291
dblp:conf/mss/KangBCLNM15
fatcat:n2kxwmmalffgncq6nr7mzbaxpe
2020-2021 Index IEEE Transactions on Computers Vol. 70
2021
IEEE transactions on computers
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Note that the item title is found only under the primary entry in the Author Index. ...
The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. ...
An Effective and Efficient Framework for Estimating the Execution Times of IO Traces on the SSD. Kang, Y., +, TC Dec. 2021 2146-2160 Credit Risk Analysis Using Quantum Computers. ...
doi:10.1109/tc.2021.3134810
fatcat:p5otlsapynbwvjmqogj47kv5qa
Memory and Storage System Design with Nonvolatile Memory Technologies
2015
IPSJ Transactions on System LSI Design Methodology
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The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance ...
The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. ...
STT-MRAM STT-MRAM is the latest generation of magnetic RAM (MRAM) [6] , [7] . ...
doi:10.2197/ipsjtsldm.8.2
fatcat:hjmdxg6wgzblpess3ejbdqa2m4
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
[article]
2018
arXiv
pre-print
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cell sensing; (3) error correction using state-of-the-art algorithms and methods; and (4) data recovery when error correction fails. ...
In this chapter, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. ...
ACKNOWLEDGMENTS The authors would like to thank Rino Micheloni for his helpful feedback on earlier drafts of the paper. They would also like to thank Seagate for their continued dedicated support. ...
arXiv:1711.11427v2
fatcat:rvnbeg4eevfa7lczf2h2ificxi
A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption
2016
Communications on Applied Electronics
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There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting ...
A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. ...
The Selective data approximation simplifies the error-protection hardware depending on the resilience levels and user-provided error tolerance of the applications. ...
doi:10.5120/cae2016652443
fatcat:hvi6m63qaredfeg3dzecvjws2e
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
2017
Journal of Low Power Electronics and Applications
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The Tag RAM on the other hand is a small section of the SRAM, which stores the addresses of the data that are stored in the SRAM. ...
Connection is established between each node through the routers using links. ...
The selective data approximation simplifies the error-protection hardware depending on the resilience levels and user-provided error tolerance of the applications. ...
doi:10.3390/jlpea7020014
fatcat:qgf4zaqltfcgpcd525wuio5dwq
Architectural Techniques for Improving NAND Flash Memory Reliability
[article]
2018
arXiv
pre-print
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Raw bit errors are common in NAND flash memory and will increase in the future. These errors reduce flash reliability and limit the lifetime of a flash memory device. ...
We analyze flash error characteristics and workload behavior through experimental characterization, and design new flash controller algorithms that use the insights gained from our analysis to improve ...
conducted on the reliability of real PCM, STT-RAM, RRAM, and memristor chips. ...
arXiv:1808.04016v1
fatcat:fotned4yajc2xmaoezwjdrgypu
2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39
2020
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Deng, J., +, TCAD Oct. 2020 3123-3127
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. ...
Gao, C., +, TCAD Oct. 2020 2230-2239
AxFTL: Exploiting Error Tolerance for Extending Lifetime of NAND Flash
Storage. ...
doi:10.1109/tcad.2021.3054536
fatcat:wsw3olpxzbeclenhex3f73qlw4
Big Computing: Where are we heading?
2018
EAI Endorsed Transactions on Scalable Information Systems
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As the complexity of computation is going to rise in the future. ...
This paper presents the overview of the current trends of Big data against the computing scenario from different aspects. ...
It is called soft errors in Big computing systems. In addition, DRAM (dynamic RAM) errors lead to undetected errors. Those errors results in incorrect answer calculation. ...
doi:10.4108/eai.13-7-2018.163972
fatcat:h7dtabdx6fdolbfez3h57s463i
Research Problems and Opportunities in Memory Systems
2014
Supercomputing Frontiers and Innovations
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We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory. ...
The memory system is a fundamental performance and energy bottleneck in almost all computing systems. ...
Acknowledgments The source code and data sets of some of the works we have discussed or alluded to (e.g., [9, 86, 97, 111, 153, 166, 196] ) are available under open source software license at our research ...
doi:10.14529/jsfi140302
fatcat:2zfa7zk3qjgohdsgxmkkqaamuu
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