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Equivalence Checking of Arithmetic Circuits on the Arithmetic Bit Level
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Index T erms-Arithmetic bit lev el, arithmetic circuit, datapath v erification, equiv alence checking, formal hardware v erification, multiplier. ...
Once the arithmetic bit-lev el representation of the circuit is obtained, equiv alence checking can be performed using simple arithmetic operations. ...
., Billerica, MA) for fruitful discussions and for providing the multiplier examples generated by commercial synthesis tools. ...
doi:10.1109/tcad.2004.826548
fatcat:ryy6ingbrvg37p4ogwho6z2jd4
Self-Referential Verification for Gate-Level Implementations of Arithmetic Circuits
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Verification of gate-level implementations of arithmetic circuits is challenging for a number of reasons: the existence of some hard-to-verify arithmetic operators, the use of different operand ordering ...
We propose a self-referential functional verification approach which uses the gate-level implementation of the arithmetic circuit under verification to verify itself. ...
Arithmetic circuits play an important role in modern high-performance VLSI datapath design. ...
doi:10.1109/tcad.2004.829799
fatcat:vdtw5p4xdjf4piaon5jzfrqbo4
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
2016
2016 Euromicro Conference on Digital System Design (DSD)
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The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. ...
In the last decade, several emerging technologies have been proposed and the time has come for studying new adhoc techniques and tools for logic synthesis, physical design and testing. ...
We also perform optimization for circuit performance parameters using the specifics of applicable technologies. 3) Realizing a nano-crossbar based synchronous state machine (SSM): By integrating arithmetic ...
doi:10.1109/dsd.2016.45
dblp:conf/dsd/AlexandrescuAAB16
fatcat:uuimqmkbhrhn7moetyaja5v5hq
Self-referential verification of gate-level implementations of arithmetic circuits
2002
Proceedings - Design Automation Conference
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In this paper, we propose a self-referential functional verification approach which uses the gate-level implementation of the arithmetic circuit under verification to verify itself. ...
Verification of gate-level implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hard-to-verify arithmetic operators (e.g. multiplication), the use of ...
ACKNOWLEDGEMENTS This research was supported in part by SRC Task 835.001 and NSF International Research Center for SoC. ...
doi:10.1145/513995.513998
fatcat:7eh7lnowgvcelkskjezv5qa7fi
Self-referential verification of gate-level implementations of arithmetic circuits
2002
Proceedings - Design Automation Conference
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In this paper, we propose a self-referential functional verification approach which uses the gate-level implementation of the arithmetic circuit under verification to verify itself. ...
Verification of gate-level implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hard-to-verify arithmetic operators (e.g. multiplication), the use of ...
ACKNOWLEDGEMENTS This research was supported in part by SRC Task 835.001 and NSF International Research Center for SoC. ...
doi:10.1145/513918.513998
dblp:conf/dac/ChangC02
fatcat:gpq565bsyzctln7abuyvs7lmra
Self-referential verification of gate-level implementations of arithmetic circuits
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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In this paper, we propose a self-referential functional verification approach which uses the gate-level implementation of the arithmetic circuit under verification to verify itself. ...
Verification of gate-level implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hard-to-verify arithmetic operators (e.g. multiplication), the use of ...
ACKNOWLEDGEMENTS This research was supported in part by SRC Task 835.001 and NSF International Research Center for SoC. ...
doi:10.1109/dac.2002.1012641
fatcat:aaobhr2sjjerhhxlf5kdkjnf34
1983 Index IEEE Transactions on Computers Vol. C-32
1983
IEEE transactions on computers
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., + , T-CSep 83 874-877
self-checking residue number arithmetic; design of error checkers.
Jenkins, W. ...
., +
T-CSep 83 809-825
totally self-checking checkers for m-out-of-(2m + 1 ) codes. ...
doi:10.1109/tc.1983.1676190
fatcat:xsogjoynp5dt7mqu6dy4tiodfq
2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38
2019
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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., +, TCAD July 2019 1278-1290 High level synthesis ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management. ...
., +, TCAD July 2019 1345-1358 Scaling Up Modulo Scheduling for High-Level Synthesis. de Souza Rosa, L., +, TCAD May 2019 912-925 TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. ...
doi:10.1109/tcad.2020.2964359
fatcat:qjr6i73tkrgnrkkmtjexbxberm
2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39
2020
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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., +, TCAD Dec. 2020 4611-4622
Tensor Optimization for High-Level Synthesis Design Flows. ...
Luan, J., +, TCAD Feb. 2020 547-551 Tensor Optimization for High-Level Synthesis Design Flows. ...
Entropy-Directed Scheduling for FPGA High-Level Synthesis. Shen, M., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS. ...
doi:10.1109/tcad.2021.3054536
fatcat:wsw3olpxzbeclenhex3f73qlw4
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance
2017
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
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Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging ...
These packages are on logic synthesis that aims to implement Boolean functions with nanocrossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence ...
We focus on a particular decomposition method that gives rise to the bounded-level logic networks called P-circuits [7] . ...
doi:10.23919/date.2017.7926998
dblp:conf/date/AltunCT17
fatcat:q2ducy4y2fc3hcfjqhc2dz3m3y
Long Residue Checking for Adders
2012
2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors
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This study investigates a novel fault detection scheme for fast adders, long residue checking (LRC), which has substantive advantages over all previous separable approaches. ...
In-house circuits are used for residue checking; the baseline adders are taken from a high-performance cell-based arithmetic unit library [6] . ...
All circuits are compiled with high mapping effort and options consistent with an areaoptimized implementation. Dual-rail encoded checkers are used to create totally self-testing designs. ...
doi:10.1109/asap.2012.31
dblp:conf/asap/SullivanS12
fatcat:2rnmt65qurcn5cppg37vxq2eq4
High-level synthesis for testability
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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We also include an overview of high-level synthesis techniques to assist high-level ATPG. 33rd Design Automation Conference ® ...
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations. ...
Originally, synthesis for testability identified gate level optimizations that could preserve or enhance circuit testability for a selected fault class without the need for more specific testability insertion ...
doi:10.1145/240518.240543
dblp:conf/dac/WagnerD96
fatcat:fj4kn2fit5aw5kyyufgwjcq6rm
Simulation and Verification of Self Test 16Bit Processor
2011
International Journal of Computer Applications
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Keywords Register transfer level, Reduced instruction set computer, Very high speed integrated circuit hardware description language , Arithmetic logic unit, Field programmable gate array. ...
All the modules in the design are coded in VHDL (very high speed integrated circuit hardware description language) to ease the description, verification, simulation and hardware implementation. ...
Logic synthesis and optimization uses optimization techniques to derive optimized circuits. Physical design determines how to implement the optimized circuit in a FPGA chip. ...
doi:10.5120/2394-3180
fatcat:bdhebxpeabb2rai5ni2rmp6yxe
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
[article]
2024
arXiv
pre-print
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2024 pre-print arXiv:2403.07257v1 fatcat:nsowxbwrqncknifg4c4plmj4p4
Such an AI4EDA approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. ...
This paper argues for a paradigm shift from AI4EDA towards AI-native EDA, integrating AI at the core of the design process. ...
Bridging this gap between high-level and low-level circuit representations has been a longstanding challenge for the EDA community. ...
arXiv:2403.07257v2
fatcat:6ema3cy7zberpemmbvenbmumsy
Logic synthesis and testing techniques for switching nano-crossbar arrays
2017
Microprocessors and microsystems
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The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. ...
In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. ...
The standard CMOS synthesis is typically performed with Sum of Products (or SOP) minimization procedures, leading to two-level circuits. ...
doi:10.1016/j.micpro.2017.08.004
fatcat:rapt2rcyljf3li3zgl2flyenqu
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