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Area-efficient synthesis of fault-secure NoC switches
2014
2014 IEEE 20th International On-Line Testing Symposium (IOLTS)
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This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect ...
Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. ...
This paper proposes a hybrid method to synthesize an area efficient fault-secure NoC switch for any single point combinational or transition delay fault in the switch or interconnect links, irrespective ...
doi:10.1109/iolts.2014.6873662
dblp:conf/iolts/DalirsaniKW14
fatcat:7vgxhaoa6ba6lnaub3vhihm3nu
Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA
2019
International journal of recent technology and engineering
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The synthesis results includes chip area, and maximum operating frequency over Artix-7 FPGA technology. Outcomes are tabulated and they show a marked improvement over previous cases. ...
The proposed hardware architecture of NoC-Router includes Input registers (which store five -port inputs with Fault injection), Error Correction Code (that encodes the input data) followed by packet formation ...
Fig. 5 . 5 Comparison Analysis of Area utilizationFrom the synthesis results, the maximum operating frequency of Fault free NoC Router with different NoC sizes includes Single Router, Mesh 2x2, Mesh 3x3 ...
doi:10.35940/ijrte.c4239.098319
fatcat:civ7ev5yobbzlgtjoyph2ulufm
Table of contents
2021
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Realization of Logic Functions Using Switching Lattices Under a Delay Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Cheng 2142 System-Level Design PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
doi:10.1109/tcad.2021.3108338
fatcat:ejmvzriq3nfvpc3lj4s43ietoe
NOC'S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency
2020
International Journal of Advanced Trends in Computer Science and Engineering
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To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia ...
Many of the NoC's has buffered and bufferless routers to optimize the area, power consumption and latency. ...
In [7] , a fault-tolerant solution for a bufferless NoC is presented to secure it from both transient and permanent faults on the links. ...
doi:10.30534/ijatcse/2020/240932020
fatcat:kj4yllfklffqrjuaipr2c26jyy
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture
2011
2011 Design, Automation & Test in Europe
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The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. ...
At-speed testing of stuck-at faults can be performed in less than 1200 cycles regardless of their size, with an hardware overhead of less than 11%. ...
With respect to previous work, we claim a more efficient use of NoC structural redundancy for testing and diagnosis purposes through the use of a cooperative testing framework. ...
doi:10.1109/date.2011.5763109
dblp:conf/date/StranoGLFGB11
fatcat:ilsnjuwfnjeencfyuui6ef5baa
Optimization of re-configurable multi-core processors and security based on field programmable gate arrays
2024
Indonesian Journal of Electrical Engineering and Computer Science
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In the proposed work, the security level has been taken care of in three different stages such as data integrity, data authentication, and private and public keys encryption and decryption. ...
algorithms using secure hash algorithm (SHA-256) bits and advanced encryption standard (AES). ...
The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. ...
doi:10.11591/ijeecs.v33.i1.pp568-580
fatcat:p2e6id4enngqnmxorsid5ugrua
2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40
2021
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. ...
., +, TCAD April 2021 735-747 STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utiliza-TCAD March 2021 533-546 A Data-Driven Asynchronous Neural Network Accelerator. ...
of Secure Nonvolatile Memories. ...
doi:10.1109/tcad.2021.3136047
fatcat:ppooj4g65nc2zonj7szclerc2y
A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities
2021
Micromachines
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However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications' requirements generates ...
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/mi12020183
pmid:33673049
fatcat:mwlekxzfpfhwhbegwwyio4kaaq
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
2020
Sensors
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Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. ...
A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. ...
The reliability of NoC is one of the key issues. This paper proposed efficient techniques to improve the reliability of an NoC router against permanent faults. ...
doi:10.3390/s20185355
pmid:32962030
pmcid:PMC7570890
fatcat:p3uqply7svc6zhmc4oxxhw6vbu
A flexible design of network on chip router based on handshaking communication mechanism
2009
2009 14th International CSI Computer Conference
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Communication portion in the power consumption of System on Chip can be up to 50% of the whole power of consumption of the chip. ...
In addition, the proposed router uses low resource utilization percentage of FPGA and ASIC. ...
These fields can be put in the main frame as the redundant fields in order to increase the controllability, fault tolerance, security and some other issues like these. ...
doi:10.1109/csicc.2009.5349425
fatcat:6svqnu7f7fg6tna67q4ykzeofu
ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks
[article]
2023
arXiv
pre-print
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An important class of security vulnerabilities involves a rogue foundry reverse-engineering the NoC topology and routing logic. ...
Our approach provides provable redaction of NoC functionality: switch configurations induce a large number of legal topologies, only one of which corresponds to the intended topology. ...
A sensitive security asset in NoC-based designs is the topology of the NoC itself. ...
arXiv:2307.05815v1
fatcat:apwrnydsa5e5pjkeqcgrfipz7u
Low power network on chip architectures: A survey
2020
Computer Science and Information Technologies
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This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between ...
Use of power should be diminished in every region of network chip architecture. ...
Based on a package and flute switching scheme, NoC provides easy data transfer which provides high throughput and efficiency [28] . ...
doi:10.11591/csit.v2i3.p158-168
fatcat:rzmirvcyxfao7pu3k2nxsjmhzy
A Survey on Security Mechanisms for NoC-based Many-Core SoCs
2021
Journal of Integrated Circuits and Systems
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This survey discusses three security-related issues: the secure admission of applications, the prevention of resource sharing during their execution, and the safe access to external devices. ...
A secure application that processes sensitive data may have its security harmed by a malicious process. ...
This NoC has dual switching, the packet switching is reserved to secure communications. Consequently, the circuit switching is destined to common packets transmission. ...
doi:10.29292/jics.v16i2.485
fatcat:vc7hgae5arhxvmko2obif4lwl4
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
2014
Journal of Parallel and Distributed Computing
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of 3D-NoC systems while ensuring fault-tolerance. ...
In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance ...
The majority of the fault-tolerant solutions were proposed for 2D-NoC systems. Some of them added restrictions to the number of faults as a security requirement for their systems. ...
doi:10.1016/j.jpdc.2014.01.002
fatcat:4t3hluctovcjzgjrttxlb6m3b4
Design and Simulation of Ring Network-on-Chip for Different Configured Nodes
2022
Computers Materials & Continua
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For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. ...
NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. ...
The network-on-chip attacks detection and security can be addressed by embedding the security algorithms so that the NoC can be applicable for high-speed communication and security requirements such as ...
doi:10.32604/cmc.2022.023017
fatcat:xlvxgfd2ofhctnkbjy7fxmzqie
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