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Improving the schedule quality of static-list time-constrained scheduling (poster paper)

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Published:01 January 2000Publication History

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References

  1. 1.D. D. Gajski et.al. "High-Level Synthesis: Introduction to Chip and System Design". Kluwer Academic Publishers, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.J. Vanhoof, G. Goosens et al. "High-Level Synthesis for Real-Time Digital Signal Processing". Kluwer Academic Publishers, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3.S. Govindarajan and R. Vemuri. "Cone-Based Clustering Heuristic for List Scheduling Algorithms". In Proc. of European Design & Test Conference (ED&TC), pages 456-462, March 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.E Kollig, B. M. A1-Hashimi, and K. M. Abbott. "Efficient scheduling of behavioral descriptions in high-level synthesis". In lEE Proc. of Computers and Digital Tech., vol. 144(2), pages 75-82, March 1997.Google ScholarGoogle ScholarCross RefCross Ref
  5. 5.I.Ouaiss, et al. "An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures". In Proc. of the Reconfig. Arch. Workshop 1998, LNCS 1388, pages 31-36.Google ScholarGoogle Scholar

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  1. Improving the schedule quality of static-list time-constrained scheduling (poster paper)

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          cover image ACM Conferences
          DATE '00: Proceedings of the conference on Design, automation and test in Europe
          January 2000
          707 pages
          ISBN:1581132441
          DOI:10.1145/343647

          Copyright © 2000 ACM

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          Publication History

          • Published: 1 January 2000

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