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Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method

Published:30 May 2018Publication History

ABSTRACT

Split manufacturing of integrated circuits (IC) was proposed as a possible defense against security issues arising from the use of potentially untrusted foundries. However, split manufactured designs were shown to be vulnerable to a new form of attack known as the proximity attack which attempts to reverse engineer the BEOL (Back End of Line) signals. Hence, care must be exercised in identifying the BEOL signals and their placement and routing. In this paper, we present a secure BEOL signal selection algorithm to defeat proximity attacks. Our method is based on two novel features: First, we introduce a new metric for signal selection based on the effect each signal has on the outputs. Second, we use a multiway partitioning algorithm to find a 'secure' cut-set which is the set of signals assigned to the BEOL layers. Our approach increases the number of BEOL nets while minimizing the impact on performance. We present experimental results which show significant improvement in security (on average by 800%) with only a modest effect on performance (less than 4% on average).

References

  1. S. Reda A. B. Kahng and Q. Wang. 2005. Architecture and details of a high quality, large-scale analytical placer 2005 ICCAD. San Jose, California, 891--898. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. U. V. Catalyurek. 1999. Hypergraph Models for Sparse Matrix Partitioning and Reordering. Ph.D. Dissertation. bibinfoschoolComputer Engineering and Information Science Bilkent University, Columbus, Ohio. http://bmi.osu.edu/umit/software.html tempurlGoogle ScholarGoogle Scholar
  3. Charles M. Fiduccia and Robert M. Mattheyses. 1982. A linear-time heuristic for improving network partitions 19th DAC. Las Vegas, Nevada, 175--181. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. C. Zhang G. S. Rose Y. Pino O. Sinanoglu J. Rajendran, H. Zhang and R. Karri. 2015. Fault Analysis-Based Logic Encryption. IEEE Trans. Computers Vol. 64 (2015), 410--424.Google ScholarGoogle ScholarCross RefCross Ref
  5. O. Sinanoglu J. Rajendran, Y. Pino and R. Karri. . 2012. Logic Encryption: A Fault Analysis Perspective. In 2012 DATE. Munich, Germany, 953--958. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. R.W. Jarvis and M.G. McIntyre. 2007. Split manufacturing method for advanced semiconductor circuits. (27 March. 2007).Google ScholarGoogle Scholar
  7. H. Ekin Sumbul Q. Zhu F. Franchetti K. Vaidyanathan, R. Liu and L. T. Pileggi. 2014. Efficient and secure intellectual property (IP) design with split fabrication 2014 IEEE International Symposium on HOST. Arlington, VA, 13--18.Google ScholarGoogle Scholar
  8. J. Hu W. Mak L. Feng, Y. Wang and J. Rajendran. 2017. Making Split Fabrication Synergistically Secure and Manufacturable 2017 ICCAD. Irvine, California, 313--320. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. H. Yalcin M. C. Hansen and J. P. Hayes. 1999. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. IEEE Trans. DTC Vol. 16 (1999), 72--80. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M. Sika M. Bajura M. Jagasivamani, P. Gadfort and M. Fritze. 2014. Split-fabrication obfuscation: Metrics and techniques 2014 IEEE International Symposium on HOST. Arlington, VA, 7--12.Google ScholarGoogle Scholar
  11. J. Rajendran M. Rostami, F. Koushanfar and R. Karri. 2013. Hardware security: threat models and metrics. In 2013 ICCAD. San Jose, California, 819--823. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. U. Schlichtmann P. Spindler and F. M. Johannes. 2008. Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Mode. IEEE Trans. on CAD Vol. 27 (2008), 1398--1411. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. Rajendran, O. Sinanoglu, and R. Karri. 2013. Is split manufacturing secure?. In 2013 DATE. Grenoble, France, 1259--1264. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Squillero. 2017. ITC'99 Benchmarks. (2017). deftempurl%https://github.com/squillero/itc99-poli tempurlGoogle ScholarGoogle Scholar
  15. R. Torrance and D. James. 2011. The state-of-the-art in semiconductor reverse engineering 48th DAC. San Diego, CA, 333--338. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, and L. Pileggi. 2014. Building trusted ICs using split fabrication. In 2014 IEEE International Symposium on HOST. Arlington, VA, 1--6.Google ScholarGoogle Scholar
  17. N. Viswanathan and C. C. N. Chu. 2005. FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. on CAD Vol. 24 (2005), 722--733. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Y. Xie, C. Bao, and A. Srivastava. 2015. Security-Aware Design Flow for 2.5D IC Technology TrustED@CCS. Denver, CO, 31--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. J. Hu Y. Wang, P. Chen and J. Rajendran. 2016. The Cat and Mouse in Split Manufacturing. In 2016 DAC. Austin, Texas, 1--6. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. J. Hu Y. Wang, P. Chen and J. Rajendran. 2017. Routing Perturbation for Enhanced Security in Split Manufacturing 2017 ASP-DAC. Chiba, Tokyo, 505--510.Google ScholarGoogle Scholar
  21. P. Yang and M. Marek-Sadowskae. 2016. Making Split-Fabrication More Secure. In 2016 ICCAD. Austin, Texas, 1--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. T. Ho Z. Chen, P. Zhou and Yier Jin. 2016. How secure is split manufacturing in preventing hardware trojan? 2016 IEEE AsianHOST. Yilan, Taiwan, 1--6.Google ScholarGoogle Scholar

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          cover image ACM Conferences
          GLSVLSI '18: Proceedings of the 2018 on Great Lakes Symposium on VLSI
          May 2018
          533 pages
          ISBN:9781450357241
          DOI:10.1145/3194554

          Copyright © 2018 ACM

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          Publication History

          • Published: 30 May 2018

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          GLSVLSI '18 Paper Acceptance Rate48of197submissions,24%Overall Acceptance Rate312of1,156submissions,27%

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