ABSTRACT
Recent studies have shown that Phase Change Memory faces significant write disturbance (WD) when scaling in deep submicron regime, i.e., resetting a cell may disturb the values of its adjacent cells if these cells are in amorphous state. A preventive approach to mitigate WD errors is to allocate sufficient inter-cell thermal band. However, this approach greatly reduces chip capacity due to low cell density. A cost effective approach VnC (verify-and-correct), relies on Verification after each write and Correction if errors do happen. Simple VnC improves chip capacity but introduces large performance degradation.
In this paper, we propose to exploit the cell level write imbalance to mitigate WD errors. A memory line is often split into cell groups so that the cells within one group are written synchronously. We observe that only few cell groups are critical, which prolong write latency and degrade system performance. By rescuing the disturbance errors from critical groups with unused Error Correction Pointer(ECP) entries, we can greatly minimize the VnC impact on performance. The experimental results show that our proposed scheme effectively eliminates VnC overhead with minimal hardware adjustments.
- Pin tool. https://software.intel.com/en-us/articles/pintool.Google Scholar
- S. J. Ahn, Y. Song, et al. Reliability perspectives for high density pram manufacturing. In IEDM, 2011.Google ScholarCross Ref
- A. R. Alameldeen and D. A. Wood. Adaptive Cache Compression for High-Performance Processors. In ISCA, 2004. Google ScholarDigital Library
- M. Awasthi, M. Shevgoor, et al. Efficient scrub mechanisms for error-prone emerging memories. In HPCA, 2012. Google ScholarDigital Library
- C. Bienia, S. Kumar, et al. The parsec benchmark suite; Characterization and architectural implications. In PACT, October 2008. Google ScholarDigital Library
- Y. Choi, I. Song, et al. A 20nm 1.8v 8gb pram with 40mb/s program bandwidth. In ISSCC, 2012.Google ScholarCross Ref
- Y. Du, M. Zhou, et al. Bit mapping for balanced pcm cell programming. In ISCA, 2013. Google ScholarDigital Library
- K. Fang, L. Chen, et al. Memory architecture for integrating emerging memory technologies. In PACT, 2011. Google ScholarDigital Library
- L. Jiang, Y. Zhang, et al. Mitigating write disturbance in super dense phase change memory. In DSN, 2014. Google ScholarDigital Library
- B. Kim, Y. Song, et al. Current status and future prospect of phase change memory. In ASICON, 2011.Google Scholar
- B. C. Lee, E. Ipek, et al. Architecting phase change memory as a scalable dram alternative. In ISCA, 2009. Google ScholarDigital Library
- K. Lee, C. Kwak, et al. Nonvolatile memory device and related methods of operation, Jan. 25 2011. US Patent 7,876,609.Google Scholar
- S. Lee, M. Kim, et al. Programming disturbance and cell scaling in pcm: for up to 16nm based 4f2 cell. In VLSIT, 2010.Google Scholar
- J. Liu, B. Jaiyen, et al. Raidr: Retention-aware intelligent dram refresh. In ISCA, 2012. Google ScholarDigital Library
- M. K. Qureshi, M. M. Franceschini, et al. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA, 2010.Google ScholarCross Ref
- M. K. Qureshi, V. Srinivasan, et al. Scalable high performance main memory system using phase-change memory technology. In ISCA, 2009. Google ScholarDigital Library
- N. H. Seong, D. H. Woo, et al. SAFER: Stuck-At-Fault error recovery for memories. In MICRO, 2010. Google ScholarDigital Library
- S. Schechter, G. H. Loh, et al. Use ecp, not ecc, for hard failures in resistive memories. In ISCA, 2010. Google ScholarDigital Library
- C. Villa, D. Mills, et al. A 45nm 1gb 1.8v phase-change memory. In ISSCC, 2010.Google ScholarCross Ref
- W. Zhang and T. Li. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In DSN, 2011. Google ScholarDigital Library
- P. Zhou, B. Zhao, et al. A durable and energy efficient main memory using phase change memory technology. In ISCA, 2009. Google ScholarDigital Library
Index Terms
- Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory
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