Ranga Vemuri
- 1.G. Birtwistle and P. A. Subrahmanyam (eds.), VLSI specsficatson, vemfication, and synthesis, Kluwer Academic Publishers, 1988 edition.Google Scholar
- 2.R. Camposano and W. Wolf, Trends sn High-Level Synthesis, Kluwer, Norwcll, Mass., 1991.Google Scholar
- 3.F. Corella, R. Camposano, R. Berganasehi and M. Payer, "Verification of Synchronous Sequential Circuits Obtained from Algebraic Specifications", CHDL '91, pp. 209-227, North-Halland Pubs., 1991.Google Scholar
- 4.W. J. Cullyer, "Implementing safety critical systems: The VIPER microprocessor", pp. 1-26, in {1}.Google Scholar
- 5.S. Devadas and K. Keutzer, "An Automata-Theoretic Approch to Behavior Equivalence", pp. 30-33, 1990Google Scholar
- 6.S. Devadas, H. T. Ma and A. R. Newton, "On the Verification of Sequential Machines at Differing Levels of Abstraction'J, IEEE Transactions on Computer-Aided Design, vol. 7, no. 6, pp. 713- 722, June 1988.Google ScholarDigital Library
- 7.P. J. Drongowski, "An organ!,zation-level story board for agent - A VLSI designer s assistant, Internal Report, DSRG, CES Sept, Case Western Reserve University, Jan 198T.Google Scholar
- 8.R. Dutta, J. Roy, and R. Vemuri, "Distributed Design-Space Exploration for High-Level Synthesis Systems", in Proc. of ~9th Design Automatson Conference, June, 1992. Google ScholarDigital Library
- 9.R. Ernst and J. Bhasker, "Simulation-based verification for high-level synthesis", IEEE Design fit Test of Computers, Vol. 17, pp. 14-20, 1991. Google ScholarDigital Library
- 10.T. E. Fuhrman and D. E. Thomas, "Verification of High Level Synthesis Designs through Gate Level Simulation of Compiled Module Implementations~, Workshop on High Level Synthesis, Kennebunkport, Maine, October 15-18, 1989.Google Scholar
- 11.D. D. Gajski (ed.), "Silicon Compilatson", Addison-Wesley Publishing Company, 1988.Google Scholar
- 12.G. Gopalakrihnan et. al,, "Combining Verification and Simulation", C. Sequin (ed.), Advanced Research in VLSI, pp. 323-339, MIT Press, 1991. Google ScholarDigital Library
- 13.W. A. Hunt Jr., "FM8501: A verified microprocessor", Tech Itep $7, Institute .for Computsn9 Sczence, Univ of Texas at Austin, Feb 1986.Google Scholar
- 14.L. J. Hafer and A. C. Parker, "Automated synthesis of digital hardware", IEEE Tran. Computers, Feb 1982.Google ScholarDigital Library
- 15.High-Level Synthesis Benchmark Clearing House, maintained Ib~pN. Dutt at UC Irvine. Our sources were in HardwareC orGoogle Scholar
- 16.R. Jain et al., "An Integrated CAD System for Algorithm- Specific IC Design", IEEE Transactions on Computer-Aided Design, Vol. 10, No. 4, pp. 447-463, April 1991.Google ScholarDigital Library
- 17.R. Join and B. Richards, LagerlV users manual, University of California at Berkeley.Google Scholar
- 18.G. Jennings, "An Exercise in VHDL Timing Backannotation', CHDL '91, pp. 63-?5, North-Holland Pubs., 1991.Google Scholar
- 19.K. W. Lai and D. P. Siewiorek, "Functional Testing of Digital Systems", Proc. 20th Design Automation Conference, june, 1983 Google ScholarDigital Library
- 20.R. Lipsett, C. Schaefer, and C. Ussery, VHDL : Hardware de. scrsptson and dessgn, Kluwer Academic Publishers, 1989 edition. Google ScholarDigital Library
- 21.P. Mamtora, "Functional Validation of a High-Level Synthesis System Through Simulation and Test Bench Compilation", M.S. Thesis, University of Cincinnati, 1992.Google Scholar
- 22.M. C. McFarland, "The VT: A Database for Automated Digital Design", DRC-01-4-80, Design Research Center, Carnegie-Mellon University, December, 1978.Google Scholar
- 23.F. Prosser and D. Winkel, The Art ofDigstalDesign, Prentice- Hall, 1987.Google Scholar
- 24.J. Roy, N. Kumar, R. Dutta and R. Vemuri, "DSS : A Distributed high-level Synthesis System", IEEE Design f~ Test of Computers, Vol. 9, No. 2, June 1992, pp.18-32. Google ScholarDigital Library
- 25.J. Roy and R. Vemuri, "Appropriate Usage of VHDL" The Synthesis Point of View", Tech. Memo TM-DDE-89-08~ Dept. of Electrical and Computer Engineering, University of Cincinnati, Dec 1989 (revised April 1990, May 1990).Google Scholar
- 26.J. Roy and R. Vemuri, "The VSS Intermediate Format (VIF)", Design Memo, Lab. for Digital Design Environments, Univermty of Cincinnati, Feb, 1991.Google Scholar
- 27.J. Roy and R. Vemuri, "Controller Implementation for Communicating and Concurrently Executing Processes", ECE-DDE- 92-13, Dept. of ECE, University of Cimcinnati, Ohio, 1992.Google Scholar
- 28.D. Siewiorek, C. Bell and A. Newell, Computer structures: Pr, nczples and examples, McGraw-Hill, 1971. Google ScholarDigital Library
- 29.User's Manual on Waveform and Vector Exchange Specification, IEEE Standard 10~9.1.Google Scholar
- 30.R. Vemuri et al., "Benchmarks for High-Level Synthesis,", Tech. Report ECE-DDE-91-11, Dept. of ECE, University of Cinicinnati, Ohio, June, 1991.Google Scholar
- 31.R. Vemuri et. al., "An Integrated Multicomponent Synthesis Environment for Multichip Modules," Computer, Special Issue on Multichip Modules, to appear in April 1993. Google ScholarDigital Library
- 32.D. Verkest, L. Claesen, and H. De Man, "On the Use of Foyer- Moore Theorem Prover for Correctness Proofs of Parametermed Hardware Modules" in L.J.M. Claesen (ed.), Formal VLSI Specification and Synthesis, pp. 99-116, North-Holland, 1990.Google Scholar
- 33.R. Vutukuru "Test bench compilation for syntheiszed multicomponent designs" Master's Thesis, University of Cincinnati, 1992.Google Scholar
- 34.(M. Yoeli ~ed.), Formal Verification of Hardware Design, IEEE Computer Society Press, 1991. Google ScholarDigital Library
Index Terms
- Experiences in functional validation of a high level synthesis system
Recommendations
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective
High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow ...
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96: Proceedings of the 9th international symposium on System synthesisThe importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...
High-Level Synthesis: Past, Present, and Future
Editor's note:This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, ...
Comments